Superjunction device and method of manufacturing the same

Abstract

The invention discloses a superjunction device, which is provided with a protective epoxy film surrounding the charge flow area, the aspect ratio of the contact hole in the transition area is greater than or equal to the aspect ratio of the contact hole in the charge flow area, and the tungsten The filling process of the plug realizes reliable filling of contact holes with different aspect ratios at the same time, the width of the P-type well is smaller than that of the P-type pillar, and a graded junction diode is formed between the P-type well and the N-type region. The invention also discloses a manufacturing method of the super junction device. The invention can reliably fill the contact hole in the transition region when the aspect ratio is relatively high, can reduce the photolithography level, and is also conducive to the layout of the contact hole according to the device requirements, and at the same time ensures that the anti-avalanche breakdown capability of the device is not affected. The impact of the contact hole process in the transition region can reduce the impact of the P-type well on the width of the N-type region at the position of the channel region, so that the on-resistance of the device is reduced; the nonlinearity of the output capacitance of the device can be improved, and the EMI issues in device applications.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a super junction device; the invention also relates to a method for manufacturing the super junction device. Background technique [0002] In existing superjunction devices, there are alternately arranged P-type columns and N-type columns in the charge flow region. Taking strip-shaped P-N columns that are alternately arranged P-type columns and N-type columns as an example, each N There is a polysilicon gate above the pillar, which can partially cover the surrounding P pillars or not. There is a P-type well (PWell) above each P-pillar, and there is an N+ source region in the P-type well. There is a contact hole, the source metal is connected to the source region through the contact hole, the source metal is connected to the P region, that is, the P-type well, through a high-concentration P+ contact region, and the source metal is the front metal laye...

AI Technical Summary

Problems solved by technology

[0004] For ease of design, or in order to reduce the number of photolithography, in the case of using the thick field oxide film as self-alignment and performing source region ion implantation, at least part of the P-type ring in the transition region needs to be covered by the thick field oxide film , so the aspect ratio of the contact hole on the region covered by the thick oxide film will be greater than the minimum aspect ratio of the contact hole in the charge flow region, wherein the contact hole in the charge flow region only needs to pass through the interlayer film, and the transition region The contact hole on the area covered by the thick oxide film needs to pass through the interlayer film and the thick oxide film at the same time, so the aspect ratio of the contact hole on the area covered by the thick oxide film will be greater than that of the charge flow area. The minimum aspect ratio of the contact hole; and in the existing technology, when the metal deposition is the manufacturing process of Ti, TiN and ALCu, Ti, TiN and ALSiCu, the coverage of the metal to the metal contact hole is limited, and the height and width If the hole is higher than 0.5, metal pinholes will appear during metal filling, causing performance and reliability problems of the device

[0005] On the other hand, when the step (Pitch) of the super junction MOSFET is not shortened, the size of the N-type drift region between the P-type pillars is continuously reduced, so the implanted region of the P-type well is greater than or equal to the P-type In the case of the width of the pillar, the size of the effective N-type region at the channel surface is getting smaller and smaller, which seriously affects the specific on-resistance of the device

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