Manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device, and relates to a manufacturing technology of semiconductor integrated circuits. The semiconductor device comprises a substrate, wherein a plurality of polycrystalline silicon gate structures are formed on the substrate and spacer protection structures are formed on spacers of the plurality of polycrystalline silicon gate structures. The manufacturing method comprises the steps of forming a first dielectric layer through an HARP DEP process, wherein the first dielectric layer covers the polycrystalline silicon gate structures and gaps between the polycrystalline silicon gate structures; forming a second dielectric layer on the first dielectric layer through an HDP DEP process so as to enable the first dielectric layer and the second dielectric layer to form a dielectric layer zero together; and carrying out a chemical mechanical polishing process on the dielectric layer zero so as to solve a problem of metal residue on the dielectric layer at the large line width.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing technology, in particular to a manufacturing method of a semiconductor device. Background technique [0002] In the manufacturing technology of semiconductor integrated circuits, the existing dielectric layer zero chemical mechanical polishing process includes: first grind the dielectric layer zero (such as silicon dioxide) with a high-selectivity grinding liquid, stop at the silicon nitride place, and then Part of the silicon nitride is ground off with a non-selective polishing solution, but this method will cause serious dish-shaped defects in the dielectric layer of zero oxide silicon with a large line width, which will cause the metal produced under chemical mechanical polishing. Metal remains where the dishing defect occurred. In order to ensure that there is no metal residue, the method of increasing the grinding time may be used, but the silicon germanium layer at the bot...

AI Technical Summary

Problems solved by technology

In the step dielectric layer zero chemical mechanical polishing process (ILD0CMP), the dielectric layer zero 140 (such as silicon dioxide) is first ground with a high-selectivity slurry, and the grinding stops at the silicon nitride sidewall 130, and then non- The polishing liquid of the selected ratio grinds away part of the silicon nitride sidewall 130. However, since the dielectric layer zero texture formed by the HARP DEP process is relatively soft, after the dielectric layer zero chemical-mechanical polishing process (ILD0CMP), it is easy to achieve a large line width. Severe dishing defects160 are generated at the dielectric layer zeros (such as large spacers between polysilicon gate structures)

In the step metal chemical mechanical polishing (such as ALCMP) process, a metal (such as aluminum AL) is chemically mechanically ground, but as figure 1 As shown, after the metal chemical mechanical polishing (such as ALCMP) process, there is still metal residue at the disc defect 160, and this metal residue will affect the performance of the semiconductor device

In order to remove the above-mentioned metal residues, the polishing time of the metal chemical mechanical polishing (such as ALCMP) process can be increased, but there is a risk that the silicon germanium layer 150 at the bottom will be ground to cause electrical abnormalities of the semiconductor device

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