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AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and its realization and preparation method

A two-dimensional semiconductor, logic gate circuit technology, applied in the field of nanoelectronics

Active Publication Date: 2020-11-27
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, there is no research in related directions, and this has become an urgent problem to be solved in the application of two-dimensional semiconductor material circuits in the future.

Method used

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  • AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and its realization and preparation method
  • AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and its realization and preparation method
  • AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and its realization and preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0048] Example 1. Preparation of devices for forming AND / OR logic gates based on two-dimensional semiconductor heterojunctions

[0049] like image 3 As shown, the device part of the AND / OR logic gate circuit based on the two-dimensional semiconductor heterojunction in this embodiment includes a gate electrode 0, an insulating substrate 1, and a first two-dimensional semiconductor material 2 on the insulating substrate 1. The material There is a second two-dimensional semiconductor material 3 and a third two-dimensional semiconductor material 4 above to form a vertical stack, the first metal electrode A is located above the second two-dimensional semiconductor material 3, and the second metal electrode B is located on the third two-dimensional semiconductor material 4, the third metal electrode Y is located above the first two-dimensional semiconductor material 2.

[0050] The method for preparing the device part of the above-mentioned two-dimensional semiconductor heterojunc...

Embodiment 2

[0058] Embodiment 2. Realization of an AND / OR logic gate circuit based on a two-dimensional semiconductor heterojunction

[0059] The third metal electrode of the two-dimensional semiconductor heterojunction device prepared in Example 1 is externally connected with a fixed resistor (R1 or R2) to form an AND / OR logic gate circuit. When realizing the AND logic function, one end of the external fixed resistor R1 is connected to the common electrode of the device—the third metal electrode Y, and the other end is connected to the power supply voltage V DD ,like figure 1 As shown; when implementing the OR logic function, one end of the external fixed resistor R2 is connected to the third metal electrode Y of the device, and the other end is grounded V SS ,like figure 2 shown.

[0060] For AND logic, see figure 1 , image 3 and Figure 5 In (a), the realization process is as follows: when the grid voltage V G When it is a negative value, the first two-dimensional semiconducto...

Embodiment 3

[0062] Embodiment 3. Implementation of a dual-function AND / OR logic gate circuit based on a two-dimensional semiconductor heterojunction

[0063] The third metal electrode Y of the two-dimensional semiconductor heterojunction device prepared in Example 1 is externally connected with a PMOS transistor M1, an NMOS transistor M2, and two fixed resistors R1 and R2 to form a dual-function AND / OR logic gate circuit. The PMOS transistor M1 and the NMOS transistor M2 share a gate electrode with the two-dimensional semiconductor heterojunction device. The drain terminal of the PMOS transistor M1 is connected to the common electrode of the device—the third metal electrode Y, the source terminal is connected to a fixed resistor R1, and the other end of R1 is connected to the power supply voltage V DD . The drain terminal of the NMOS transistor M2 is connected to the common electrode of the device—the third metal electrode Y, the source terminal is connected to the fixed resistor R2, and...

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Abstract

The invention discloses a 2D semiconductor heterojunction based AND / OR logic gate circuit and realization and preparation methods thereof. Two 2D semiconductor heterogeneous PN junctions with unidirectional conductivity are connected in parallel and cooperated with a fixed resistor to realize AND / OR logic functions. The grid voltage is changed to adjust the direction of the unidirectional conductivity of the 2D semiconductor heterogeneous PN junctions, so that the PN junction is changed into an NP junction. When the 2D semiconductor heterogeneous PN junctions are in different unidirectional conductivity directions, the AND and OR logic functions can be realized, namely, change between AND and OR logics can be changed by changing the grid voltage. Thus, a preparation technology of the device is simple, the circuit is easy to realize, the circuit area is reduced greatly and large-scale integration can be realized.

Description

technical field [0001] The invention belongs to the technical field of nanoelectronics, and in particular relates to a realization and preparation method of an AND / OR logic gate circuit of a two-dimensional semiconductor heterojunction. Background technique [0002] Two-dimensional materials have many remarkable physical and chemical properties, making them the frontier focus of current international material science research. Their properties are diverse and complementary, covering various types from conductors, semiconductors to insulators, including graphene, transition metal dichalcogenides, black phosphorus and boron nitride, etc. In the field of electronic devices, in recent years, two-dimensional semiconductor materials have become a very promising type of semiconductor materials in the post-Moore era due to their atomic-level thickness that can achieve ideal gate control and large band gaps that can suppress source-drain tunneling current. Especially in the field of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H03K19/20H01L21/77
CPCH01L21/77H01L27/12H03K19/20
Inventor 黄如贾润东黄芊芊陈亮
Owner PEKING UNIV
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