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Power-up checker and method for monitoring proper power-up sequence of integrated circuits

A technology of integrated circuits and checkers, applied in the field of power-on checkers, can solve the problems of voltage drop and final

Active Publication Date: 2020-08-04
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, it is not desirable for the AND gate to fall LOW at CX (i.e., Figure 1B state 154 in , where PX = 1, CX = 0, and POC = 1)) followed by a signal indicating an incorrect power-up sequence, because CX may rise and crash multiple times during normal operation of the SoC
Also, since the AND gates are powered by PX, all devices must be thick I / O devices due to the higher voltage
The voltage at CX may drop further and eventually flip the POC output, causing unintentional I / O state latching in the system

Method used

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  • Power-up checker and method for monitoring proper power-up sequence of integrated circuits
  • Power-up checker and method for monitoring proper power-up sequence of integrated circuits
  • Power-up checker and method for monitoring proper power-up sequence of integrated circuits

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Embodiment Construction

[0023] figure 2 An exemplary latch-based power-on checker (POC) circuit 200 is shown. The POC circuit 200 includes a latch 206 that includes two nodes (node ​​A 202 and node B 204) and cross-coupled inverters (A1) 210 and (A2) 212 (where node B is also coupled to the POC output 208). Unlike the AND gate implementation described above, the latch-based POC circuit 200 does not require native NFETs and is suitable for FinFET fabrication processes.

[0024] Cross-coupled inverters 210 and 212 form latches, and resistors (R1) 214 and (R2) 216 are connected to the output of each inverter to minimize the Effect of Process Skew. Buffer (A3) 218 ​​may be provided as a buffer with hysteresis to clean up any noise at the output due to the slow ramp-up of the PX supply.

[0025] Node A 202 is controlled by a first flip-flop circuit 220 and node B 204 is controlled by a second flip-flop circuit 222 .

[0026] POC 200 is included in first IC die 270 . POC output 208 controls enable c...

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Abstract

A latch-based power-on checker (POC) circuit for easing communication between different power domains (e.g., cores and input / output (I / O)) on a system-on-chip (SoC) integrated circuit (IC) Potential problems caused by incorrect power-up sequence. In one example, the core power domain with the first voltage (CX) should be powered up before the I / O power domain with the second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit generates a signal indicating an incorrect power-up sequence, which causes the I / O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX subsequently crashes while PX is still rising, the POC circuit will stay LOW until PX also crashes.

Description

[0001] References to related applications [0002] This application is a continuation of US Patent Application No. 15 / 197,589 filed on June 29, 2016, which is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to power distribution in integrated circuits (ICs), and more particularly to power-up checkers for system-on-chip (SoC) ICs with multiple power domains. Background technique [0004] A system-on-chip (SoC) integrated circuit (IC) integrates multiple components of an electronic system, such as one or more processor cores, memory blocks, external input / output (I / O) interfaces, and power management circuits, into a single chip middle. SoCs typically include at least two different power domains that operate at different frequency and voltage ranges for different components (such as a processor core (CX domain) that can utilize voltages below 1V, and that can utilize External I / O pads (PX domain) for higher voltages (...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K17/22G06F1/24
CPCH03K17/223H03K5/19G06F1/30H03K3/012H03K3/0375
Inventor W·陈C-G·谭R·贾里里泽纳里
Owner QUALCOMM INC