Substrate etching method and corresponding processing device

Abstract

The invention provides a substrate etching method. The method is performed in a plasma processing device. A substrate etched by the substrate etching method comprises a photoresist mask layer, a dielectric anti-reflection layer, a carbon hard mask layer, and a silicon oxide layer, wherein the carbon hard mask layer below the dielectric anti-reflection layer is etched with a patterned dielectric anti-reflection layer as a mask so as to form a patterned carbon hard mask layer, the plasma processing device comprises an RF source power source and an RF bias power source, the RF bias power source outputs an RF signal with frequency greater than 2MHZ when the dielectric anti-reflection layer is etched, so as to monitor etching process, when etching of the dielectric anti-reflection layer is completed, an output frequency of the RF bias power source is switched to less than 2MHZ, so as to realize etching of the carbon hard mask layer. The method has the advantages of ensuring that an etchinghole wall of the carbon mask layer is vertical and lowering opening width of an etching hole.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a substrate etching method and a corresponding processing device. Background technique [0002] In the semiconductor integrated circuit manufacturing process, a semiconductor structure is formed on a semiconductor substrate through a series of processes, such as deposition, photolithography, etching, planarization and other processes. Wherein, a photolithography process is used to form a mask pattern to define a region to be etched. The etching process is used to transfer the pattern defined by lithography to the material (metal, dielectric layer or silicon) to form the desired structure. In the current semiconductor process, in order to enhance the accuracy of the transfer, it is generally used to first The pattern formed by the photoresist layer is transferred to the dielectric anti-reflection layer (or anti-reflection layer DARC) by exposure, and then the ...

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Problems solved by technology

[0005] As a new generation of memory, 3D NAND devices are composed of several layers of etched materials, that is, amorphous carbon layers. Several holes for placing conductive materials are formed in the amorphous carbon layers. These holes are densely distributed, and the hole openings occupy The larger the area, the higher the cost; in the prior art, oxygen plasma etching is used, and the dielectric anti-reflection layer is used as a mask to etch the amorphous carbon layer below it, and the holes etched by this method The side is actually bow-shaped (low-like), and the mouth of the opening is larger than ideal and even produces distortion and aliasing, such as figure 1 As shown, which shows the cross-sectional view and top view of the carbon hard mask layer 13' after the etching is completed, it can be seen from the figure that some of the damaged openings and the inner side walls of all holes have a large inclination and are not vertical, and the opening size is relatively large , the etched deep hole morphology is not vertical, and the adjacent carbon mask layer is almost cut through, which shows that the effect is not ideal; therefore, it is necessary to provide an etching method that can ensure the verticality of each hole in the amorphous carbon layer, To ensure that the amorphous carbon layer can form more holes in the same area, thereby reducing costs

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