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Structure for improving responsivity of back-illuminated photodiode and manufacturing method thereof

A technology of photodiode and manufacturing method, applied in circuits, electrical components, semiconductor devices, etc., can solve problems such as reducing ohmic contact area, increasing diode series resistance, reducing frequency characteristics, etc., to improve specific wavelength responsivity, and improve detection. The effect of rate and sensitivity

Inactive Publication Date: 2019-03-12
THE 44TH INST OF CHINA ELECTRONICS TECH GROUP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, this method needs to occupy the ohmic contact area of ​​the active area to deposit a dielectric DBR reflective layer, reducing the ohmic contact area, which will increase the series resistance of the diode and reduce its frequency characteristics

Method used

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  • Structure for improving responsivity of back-illuminated photodiode and manufacturing method thereof
  • Structure for improving responsivity of back-illuminated photodiode and manufacturing method thereof
  • Structure for improving responsivity of back-illuminated photodiode and manufacturing method thereof

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Embodiment 1

[0054] As a specific embodiment, the present invention will be described in detail below in conjunction with the accompanying drawings and process flow. In this embodiment, the chip structure epitaxial material is grown on n + - On InP substrate, the structure see attached Figure 3-4 ,as followed:

[0055] 1) n-InP buffer layer

[0056] n-type indium phosphide (InP) buffer layer, carrier concentration ≥ 1×10 18 cm -3 , with a thickness of 0.1-1.0 μm;

[0057] 2) i-InGaAs absorption layer

[0058] Intrinsic or unintentionally doped InGaAs as the absorber layer, the carrier concentration is 15 cm -3 , the thickness is 0.4~1.2μm;

[0059] 3) n-InGaAsP gradient layer

[0060] n-type indium gallium arsenide phosphide (InGaAsP) graded layer, doping concentration ≤1×10 16 cm -3 Its growth thickness is 0.03 to 0.1 microns;

[0061] 4) n-DBR window layer

[0062] n-type distributed Bragg reflection (DBR) window layer, the DBR layer is composed of two different refractive in...

Embodiment 2

[0076] As a specific embodiment, the present invention will be described in detail below in conjunction with the accompanying drawings and process flow. In this embodiment, the chip structure epitaxial material is grown on n + - On InP substrate, the structure see attached Figure 5-6 ,as followed:

[0077] 1) n-InP buffer layer

[0078] n-type indium phosphide (InP) buffer layer, carrier concentration ≥ 1×10 18 cm -3 , with a thickness of 0.1-1.0 μm;

[0079] 2) i-InGaAs absorption layer

[0080] Intrinsic or unintentionally doped InGaAs as the absorber layer, the carrier concentration is 15 cm -3 , the thickness is 0.4~1.2μm;

[0081] 3) n-InGaAsP gradient layer

[0082] n-type indium gallium arsenide phosphide (InGaAsP) graded layer, doping concentration ≤1×10 16 cm -3 Its growth thickness is 0.03 to 0.1 microns;

[0083] 4) p-DBR window layer

[0084] The p-type distributed Bragg reflection (DBR) window layer, the DBR layer is composed of two different refractiv...

Embodiment 3

[0096] As a specific embodiment, the present invention will be described in detail below in conjunction with the accompanying drawings and process flow. In this embodiment, the epitaxial material in the present invention is grown on n + - On InP substrate, the structure see attached Figure 7-8 ,as followed:

[0097] 1) n-InP buffer layer

[0098] n-type indium phosphide (InP) buffer layer, carrier concentration ≥ 1×10 18 cm -3 , with a thickness of 0.1-1.0 μm;

[0099] 2) i-InGaAs absorption layer

[0100] Intrinsic or unintentionally doped InGaAs as the absorber layer, the carrier concentration is 15 cm -3 , with a thickness of 0.4-1.2 μm;

[0101] 3) n-InGaAsP gradient layer

[0102] n-type indium gallium arsenide phosphide (InGaAsP) graded layer, doping concentration ≤1×10 16 cm -3 Its growth thickness is 0.03 to 0.1 microns;

[0103] 4)n + -InP charge layer

[0104] n-type indium phosphide (InP) charge layer, doping concentration 1~5×10 17 cm -3 , with a thi...

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Abstract

The present invention relates to the field of semiconductor photodiodes, in particular to a structure for improving responsivity of a back-illuminated photodiode and a manufacturing method thereof. The structure includes a substrate, and absorption layer, a graded layer, a window layer, and an ohmic contact layer are grown on the substrate. A mesa-type chip structure is adopted for the structure,a surface of the mesa is covered with a passivation layer, a window of an active area is covered with a P electrode, and an N electrode is taken out from an N-type contact layer under the mesa, forming a coplanar electrode with the P electrode. In the present invention, an ohmic contact area is effectively reduced, diode series resistance is increased to reduce frequency characteristics, and the above effect on high-speed photodiode designs is more obvious.

Description

technical field [0001] The invention relates to the field of semiconductor photodiodes, in particular to a structure and a manufacturing method for improving the responsivity of a back-illuminated photodiode. Background technique [0002] In fiber optic communication systems, photodiodes are used to convert information-carrying optical signals into information-carrying electrical signals, so that subsequent circuits can process the information. According to the different ways of incident light, it can be divided into front-illuminated type, back-illuminated type and side-illuminated type. [0003] With the continuous improvement of the high-speed optical fiber communication system for the photodiode rate (≥25Gbps), the diode light receiving aperture is getting smaller and smaller (diameter≤20μm), and the difficulty of fiber coupling is becoming more and more difficult. Front-illuminated and side-illuminated photodiodes are not conducive to mass production due to the difficu...

Claims

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Application Information

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IPC IPC(8): H01L31/0216H01L31/0304H01L31/105
CPCH01L31/02161H01L31/0304H01L31/03046H01L31/105
Inventor 黄晓峰王立崔大健高新江莫才平迟殿鑫樊鹏陈伟
Owner THE 44TH INST OF CHINA ELECTRONICS TECH GROUP CORP