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Semiconductor structure and semiconductor process method

A process method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as defects, photoresist residue, and affecting product yield, so as to improve yield, The effect of avoiding defects and saving production costs

Active Publication Date: 2019-07-26
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a semiconductor process method for solving the problem of trimming the wafer before performing the photolithography process on the wafer in the prior art. The photoresist caused by processing tends to remain on the right-angled steps on the edge of the wafer, which will cause defects in the subsequent process and affect the yield of the product.

Method used

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  • Semiconductor structure and semiconductor process method
  • Semiconductor structure and semiconductor process method
  • Semiconductor structure and semiconductor process method

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Embodiment 1

[0083] see Figure 7 , the present invention provides a kind of semiconductor processing method, described semiconductor processing method comprises the steps:

[0084] 1) Provide wafers;

[0085] 2) forming a dielectric layer on the wafer;

[0086] 3) Etching the dielectric layer to form etching via holes in the dielectric layer;

[0087] 4) forming a metal interconnection layer in the etched via hole;

[0088] 5) forming a protective layer on the upper surface of the dielectric layer and the upper surface of the metal interconnection layer; and

[0089] 6) Perform edge trimming on the wafer.

[0090] In step 1), see Figure 7 Step S1 in and Figure 8 , providing a wafer 20 .

[0091] As an example, the wafer 20 may include a silicon wafer, a germanium (Ge) wafer, a silicon germanium (SiGe) wafer, an SOI (Silicon-on-insulator, silicon-on-insulator) wafer or a GOI (Germanium-on-insulator) wafer. -Insulator, germanium-on-insulator) wafer, etc.; preferably, in this embod...

Embodiment 2

[0131] see Figure 17 , the present invention also provides a semiconductor structure, the semiconductor structure includes: a wafer 20, a dielectric layer 21, the dielectric layer 21 is located on the wafer 20, and an etching through hole 23 is formed in the dielectric layer 21 a metal interconnect layer 24, the metal interconnect layer 24 at least fills the etched via hole 23; and a protective layer 25, the protective layer 25 covers the upper surface of the dielectric layer 21 and the metal interconnect The upper surface of the connecting layer 24.

[0132] As an example, the wafer 20 may include a silicon wafer, a germanium (Ge) wafer, a silicon germanium (SiGe) wafer, an SOI (Silicon-on-insulator, silicon-on-insulator) wafer or a GOI (Germanium-on-insulator) wafer. -Insulator, germanium-on-insulator) wafer, etc.; preferably, in this embodiment, the wafer 20 includes a single crystal silicon wafer.

[0133] As an example, the size of the wafer 20 may be set according to ...

Embodiment 3

[0148] Please combine Figure 2 to Figure 16 refer to Figure 18 , the present invention also provides a semiconductor structure, the semiconductor structure includes: a wafer 20; a dielectric layer 21, the dielectric layer 21 is located on the upper surface of the wafer 20, and an etching via is formed in the dielectric layer 21 hole 23; metal interconnection layer 24, the metal interconnection layer 24 is located in the etched through hole 23; chamfer 204, the chamfer 204 is located in the edge region of the wafer 20, the chamfer 204 After the metal interconnection layer 24 is formed.

[0149] As an example, the wafer 20 may include a silicon wafer, a germanium (Ge) wafer, a silicon germanium (SiGe) wafer, an SOI (Silicon-on-insulator, silicon-on-insulator) wafer or a GOI (Germanium-on-insulator) wafer. -Insulator, germanium-on-insulator) wafer, etc.; preferably, in this embodiment, the wafer 20 includes a single crystal silicon wafer.

[0150] As an example, the size of ...

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Abstract

The invention provides a semiconductor structure and a semiconductor process method. The semiconductor process method comprises the following steps of providing a wafer; forming a dielectric layer onthe wafer; etching the dielectric layer to form an etched via hole in the dielectric layer; forming a metal interconnection layer in the etched via hole; forming a protective layer on the upper surface of the dielectric layer and the upper surface of the metal interconnection layer; and trimming the wafer. The semiconductor processing method provided by the invention performs a photolithography etching process to form an etched via hole before performing a trimming process on the wafer and forms a metal interconnection layer in the etched via hole, and no photolithography process is performedafter the wafer is trimmed, and there is no photoresist residue at the corners formed after the wafer trimming process, thereby avoiding the occurrence of defects and improving the yield of the product. At the same time, it is not necessary to backfill the etched via hole before trimming the wafer, which simplifies the generation process, improves the production efficiency and saves the productioncosts.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and manufacture, and in particular relates to a semiconductor structure and a semiconductor process method. Background technique [0002] In some existing semiconductor processes, wafers need to be trimmed. For example, one of the wafers needs to be trimmed before bonding two wafers to ensure that the two wafers are trimmed. After the round bonding is completed, no peeling (Peeling) phenomenon will occur in the process of thinning the bonded structure. Then, since the wafer that has been sliced ​​will have a right-angle step in the edge region of the wafer, the existence of the right-angle step makes the photoresist (PR) spin coating process of the subsequent photolithography process on the wafer In this case, the photoresist will accumulate at the right-angle step, and the height of the photoresist accumulation at the right-angle step is several times or even ten times the thic...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L23/528
CPCH01L21/76804H01L21/76865H01L23/5283
Inventor 严孟付洋朱继锋胡思平王家文邓卫之
Owner YANGTZE MEMORY TECH CO LTD
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