1553B bus IP core and monitoring system

Abstract

The invention discloses a 1553B bus IP core. The IP core comprises a bus transceiver and a main module. The bus transceiver and the main module are integrated on an FPGA; the bus transceiver is used for receiving a bus message from a 1553B bus and forwarding the bus message to the main module. The main module is used for decoding the received bus message, analyzing whether the message is correct,acquiring attribute information and original information of each message, and packaging and storing according to a packet format. The invention also discloses a 1553B bus monitoring system, and the system comprises the IP core and a control module, and the IP core also comprises an AXI bus adapter. The control module is used for reading the stored data from the main module through AXI bus switching and sending the control instruction and the configuration information to the main module. The system is suitable for the application field of satellite electronics, and has light weight, integrationand relative independence. The IP core can serve as an IP core to be attached to an on-chip bus protocol, power consumption is low, the IP core is relatively independent and can be migrated and reused, and integration of multiple IP cores in a board is facilitated.

Description

technical field [0001] The invention relates to the application field of satellite electronics, in particular to the integration and multiplexing of IP cores in an on-chip bus protocol, and in particular to a 1553B bus IP core and a monitoring system. Background technique [0002] The MIL-STD-1553B bus is a half-duplex time-division command / response multiplexed data bus with high reliability and high flexibility. With its 1Mbps transmission rate, it is widely used in the field of low-speed communication transmission. [0003] In aerospace integrated electronics, the 1553B data bus is usually used as a data channel to connect various subsystems in satellites, spacecraft and other systems for effective transmission of scientific data and control information. 1553B bus topology such as figure 1 As shown, the A / B channel can mount one BC (bus control terminal), no more than 31 RTs (remote terminals) and one MT (monitor). [0004] BC is the initiator of messages on the bus and ...

AI Technical Summary

Problems solved by technology

At this stage, the three-in-one fusion protocol chip of bus controller, remote terminal and monitor is widely used. The monitor is often an extended function, which occupies less resources in the fusion protocol chip itself, and only one mode can be selected when working. Work, when only the monitor function is selected, a lot of resources will be idle

[0007] (2) High power consumption

Consider independent monitor design, which is mostly used in ground detection systems. There are many PC-based card designs, and at the same time, it is mainly based on high-power and high-speed bus design, such as PCI / PCIE bus, which has high power consumption and is not conducive to equipment. Intra-plate grafting

[0008] (3) Poor integration performance

In most designs, it is necessary to report that the CPU generates an interrupt at the end of each message, and the interaction with the CPU is frequent, which is not conducive to the integration of multiple IP cores on the device board.

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