1553B bus IP core and monitoring system

A bus monitoring and bus technology, applied in the field of satellite electronics applications, can solve the problems of high power consumption, frequent CPU interaction, unfavorable equipment board transplantation, etc., and achieve the effect of low power consumption

Active Publication Date: 2019-09-06
NAT SPACE SCI CENT CAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this stage, the three-in-one fusion protocol chip of bus controller, remote terminal and monitor is widely used. The monitor is often an extended function, which occupies less resources in the fusion protocol chip itself, and only one mode can be selected when working. Work, when only the monitor function is selected, a lot of resources will be idle
[0007] (2) High power consumption
Consider independent monitor design, which is mostly used in ground detection systems. There are many

Method used

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  • 1553B bus IP core and monitoring system
  • 1553B bus IP core and monitoring system
  • 1553B bus IP core and monitoring system

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Experimental program
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Embodiment 1

[0049] Implementation 1 of the present invention proposes a 1553B bus IP core, including a main module; the main module can work independently, and can flexibly be attached to multiple on-chip bus protocols. The present invention provides a design process for the AXI on-chip bus, which is convenient for final testing And other bus-controlled migration applications. The main module implements the function of 1553B filtering and monitoring, packs and stores the received information, and provides a message output interface and a message control interface.

[0050] Such as figure 2 As shown, MT is the main module. MT receives bus messages through 1553B bus transceivers, adds attribute information to each message after processing, and packs and stores them in FIFO. The functions of each unit are as follows:

[0051] (1) Configuration unit: It includes the configuration of the AXI bus slave module, HPI-AXI bridge conversion, and provides interrupt feedback and read interface.

[...

Embodiment 2

[0085] Embodiment 2 of the present invention provides a kind of 1553B bus monitoring system that comprises above-mentioned IP core, and this system also includes the control module that runs on the host computer; Also includes on the described IP core: AXI bus transfer;

[0086] The AXI bus transfer on the FPGA is the communication connection module, which can read the messages in the FIFO and read back the stored data. The communication connection module adds functions such as system-on-chip protocol interface on the basis of the main module. The control module is used to control the start and end of the work of the main module, read the stored 1553B bus information, and complete the docking communication with the CPU.

[0087] In this communication interface design, the control signal sent by the upper computer is sent and received through the HPI interface, and the information is transferred through the HPI to AXI bridge to realize the control of the IP core. The upper comp...

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Abstract

The invention discloses a 1553B bus IP core. The IP core comprises a bus transceiver and a main module. The bus transceiver and the main module are integrated on an FPGA; the bus transceiver is used for receiving a bus message from a 1553B bus and forwarding the bus message to the main module. The main module is used for decoding the received bus message, analyzing whether the message is correct,acquiring attribute information and original information of each message, and packaging and storing according to a packet format. The invention also discloses a 1553B bus monitoring system, and the system comprises the IP core and a control module, and the IP core also comprises an AXI bus adapter. The control module is used for reading the stored data from the main module through AXI bus switching and sending the control instruction and the configuration information to the main module. The system is suitable for the application field of satellite electronics, and has light weight, integrationand relative independence. The IP core can serve as an IP core to be attached to an on-chip bus protocol, power consumption is low, the IP core is relatively independent and can be migrated and reused, and integration of multiple IP cores in a board is facilitated.

Description

technical field [0001] The invention relates to the application field of satellite electronics, in particular to the integration and multiplexing of IP cores in an on-chip bus protocol, and in particular to a 1553B bus IP core and a monitoring system. Background technique [0002] The MIL-STD-1553B bus is a half-duplex time-division command / response multiplexed data bus with high reliability and high flexibility. With its 1Mbps transmission rate, it is widely used in the field of low-speed communication transmission. [0003] In aerospace integrated electronics, the 1553B data bus is usually used as a data channel to connect various subsystems in satellites, spacecraft and other systems for effective transmission of scientific data and control information. 1553B bus topology such as figure 1 As shown, the A / B channel can mount one BC (bus control terminal), no more than 31 RTs (remote terminals) and one MT (monitor). [0004] BC is the initiator of messages on the bus and ...

Claims

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Application Information

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IPC IPC(8): H04L12/40
CPCH04L12/40013H04L12/40026
Inventor 张瑞琰安军社姜秀杰周盛雨
Owner NAT SPACE SCI CENT CAS
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