Gate dielectric layer, manufacturing method of field effect transistor and field effect transistor device
A gate dielectric layer and manufacturing method technology, applied in the field of gate dielectric layer manufacturing in the high-k dielectric layer metal gate integration process, can solve the problems of device threshold voltage increase, unfavorable work function adjustment, etc., and prevent the diffusion of metal atoms , precise etching thickness and controllable etching speed
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0043] This embodiment first provides a method for processing an N-type field effect transistor using a high-k dielectric layer metal gate process. The gate structure formed by the final target is as follows: figure 1 As shown, in this embodiment, the gate dielectric layer is made of hafnium oxide material with a high dielectric constant instead of the traditional silicon oxide material, the barrier layer is made of titanium nitride material, and the metal gate is made of titanium aluminum alloy.
[0044] The manufacturing method provided in this embodiment includes the following steps:
[0045] 1. Deposition of hafnium oxide gate dielectric layer
[0046] The manufacturing and processing method of the gate dielectric layer provided in this embodiment firstly obtains the following figure 2 The gate structure shown is that a gate dielectric layer is formed on the interface layer. Other optional gate dielectric layer materials include but are not limited to hafnium oxide silic...
Embodiment 2
[0068] This embodiment provides a method for manufacturing a gate dielectric layer, the process of which is as follows Figure 5 shown, including the following steps:
[0069] 1. Deposition of hafnium oxide gate dielectric layer
[0070] 2. DPN nitrogen doping treatment
[0071] 3. Wet etching the surface of the gate dielectric layer
[0072] Among them, the gate dielectric layer deposition process and the DPN nitrogen doping process used in this embodiment are exactly the same as those in Embodiment 1. Since the DPN process is under the condition of certain parameters, after the same material is doped, the internal nitrogen The doping depth and distribution of atoms are basically unchanged. Therefore, after the DPN nitrogen doping step is completed, the obtained nitrogen atom concentration distribution on the surface of the gate dielectric layer is still as follows: Figure 4 shown.
[0073] The main difference between the manufacturing method of the gate dielectric laye...
Embodiment 3
[0076] This embodiment provides a manufacturing method for a gate dielectric layer, which is different from the manufacturing method provided in Embodiment 2. The main difference is that in this embodiment, the etching depth is selected as That is, it does not reach the peak position of nitrogen doping concentration.
[0077] When etching to this position, although the concentration of nitrogen atoms on the surface of the gate dielectric layer has not reached the peak value, the ratio of the number of nitrogen atoms located on the surface to the total number of nitrogen atoms is higher than that in Example 1, and what is the specific distance from the interface? The ability of nitrogen atoms in this depth to adjust the threshold voltage needs to be judged according to the actual situation. Therefore, technicians can still choose the manufacturing method provided in this embodiment according to the actual situation, so as to greatly improve the distribution of nitrogen atoms an...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More