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Oscillation circuit

A technique of oscillating circuits and circuits, applied in power oscillators, electrical components, adjusting electrical variables, etc., can solve the problems of circuit scale enlargement and oscillation frequency change, etc., and achieve the effect of small circuit scale and small influence of temperature

Pending Publication Date: 2019-09-20
SEIKO INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the conventional oscillation circuit 700 needs two current sources having opposite characteristics with respect to temperature, a comparator, and a reference voltage VREF such as a BGR (Band Gap Reference) circuit that does not depend on temperature. get bigger
In addition, there is a problem that the oscillation frequency fluctuates depending on the temperature when the temperature characteristic of the resistor 708 fluctuates due to manufacturing variation.

Method used

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  • Oscillation circuit
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Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0026] figure 1 It is a diagram showing an oscillation circuit 100 according to the first embodiment, and is composed of a constant current circuit 1 , a charging and discharging circuit 2 , and a control circuit 3 .

[0027] The constant current circuit 1 includes a depletion-type PMOS transistor 30 serving as a current source, enhancement-type PMOS transistors 11 and 12 serving as a current mirror circuit, and an enhancement-type NMOS transistor 21 serving as a current mirror circuit. , 22 forms. In the depletion-type PMOS transistor 30 , the source and the gate are connected to the first power supply VDD, and the drain is connected to the source of the PMOS transistor 11 . In the PMOS transistor 11 , the gate is connected to the gate of the PMOS transistor 12 , and the drain is connected to the drain and gate of the NMOS transistor 21 . The drain of the PMOS transistor 11 is referred to as a node N1. In the PMOS transistor 12 , the source is connected to the first power...

no. 2 approach

[0066] image 3 It is a diagram showing the charging and discharging circuit 2, the control circuit 3, and the waveform shaping circuit 4 of the oscillation circuit of the second embodiment. The second embodiment differs from the oscillation circuit 100 of the first embodiment in that the waveform shaping circuit 4 is provided, and is the same as the first embodiment in other respects. Description of the same parts as those of the first embodiment will be omitted.

[0067] The waveform shaping circuit 4 is composed of enhancement type PMOS transistors 15 , 16 , enhancement type NMOS transistors 25 , 26 , and inverters 51 , 52 .

[0068] In the PMOS transistor 15 , the source is connected to the first power supply VDD, the gate is connected to the node N2 , and the drain is connected to the NMOS transistor 25 and the input of the inverter 51 . In the NMOS transistor 25, the gate is connected to the node N1 of the constant current circuit, and the source is connected to the se...

no. 3 approach

[0072] Figure 4 It is a diagram showing the charging and discharging circuit 2 , the control circuit 3 , and the voltage boost circuit 5 of the oscillation circuit of the third embodiment. The third embodiment differs from the oscillation circuit 100 of the first embodiment in that the voltage boosting circuit 5 is provided, and is the same as the first embodiment in other respects. Description of the same parts as those of the first embodiment will be omitted.

[0073] The voltage boosting circuit 5 is composed of enhancement type PMOS transistors 17 and 18 .

[0074] In the PMOS transistor 17, the source is connected to the first power supply VDD, the gate is connected to the node N4, and the drain is connected to the node N2. In the PMOS transistor 18, the source is connected to the first power supply VDD, the gate is connected to the node N5, and the drain is connected to the node N3.

[0075] The operation of this embodiment will be described. After explaining the oper...

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PUM

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Abstract

The invention relates to an oscillation circuit. Provided is the oscillation circuit having a small circuit scale and little influence on the temperature of an oscillation frequency. The oscillation circuit is characterized by being provided with a constant current circuit that supplies a current based on a first depletion-mode MOS transistor; charging and discharging circuit, the present invention is provided with a first capacitor; a second capacitor; a second depletion-mode MOS transistor provided in a current path for charging the first capacitor; and a third depletion-mode MOS transistor provided in a current path for charging the second capacitor. Threshold voltages of the first to third depletion MOS transistors are the same and temperature characteristics of the threshold voltages are the same. A charging circuit that charges the first capacitor using a current based on the constant current circuit, outputs a reset signal when the charging of the first capacitor is completed, charges the second capacitor using a current based on the constant current circuit, and outputs a set signal when the charging of the second capacitor is completed; and an RS latch circuit that outputs a waveform that decreases in accordance with an input of the reset signal and increases in accordance with an input of the set signal.

Description

technical field [0001] The present invention relates to oscillator circuits. Background technique [0002] As a conventional oscillation circuit, a configuration as shown in Patent Document 1 is known. Figure 6 A conventional oscillation circuit 700 is shown. [0003] MOS transistors 702 and 704 constitute a current mirror circuit. The MOS transistor 706 controls the current I1 flowing in the current mirror circuit with the control voltage V1. Let the drain of the MOS transistor 704 be a node N6. [0004] The resistor 708 is connected between the first power supply VDD and the node N6, and flows a current I2. The capacitor 710 is connected between the node N6 and the second power supply VSS (GND). [0005] The differential amplifier 712 is input with the voltage of the node N6 and the reference voltage VREF, and its output is connected to the pulse generator 716 . The pulse generator 716 outputs a reset signal and an oscillating output signal OUT, the output of the res...

Claims

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Application Information

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IPC IPC(8): H03B5/04H03B5/12
CPCH03B5/04H03B5/1228G05F3/262H03K3/0231G05F3/245H03K3/011H03K3/0375H03K3/356008H03K3/354H03K3/0315H02M3/07G05F1/567H03B5/24
Inventor 渡边考太郎
Owner SEIKO INSTR INC
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