Carbon nanotube three-dimensional fin transistor and preparation method thereof

Abstract

The invention discloses a carbon nanotube three-dimensional fin transistor and a preparation method thereof. The carbon nanotube three-dimensional fin transistor is a transistor structure based on anembedded gate fin with Dirac two-dimensional semimetal as source and drain electrodes. The short channel effect of the carbon nanotube three-dimensional fin transistor can be reduced while the fin transistor has a small size, since the Dirac two-dimensional semimetal has a two-dimensional ultra-thin structure, the electrostatic shielding effect of the source and drain electrodes for a gate electrode in the gate structure can be reduced when the Dirac two-dimensional semimetal is used as source and drain electrode materials of the carbon nanotube three-dimensional fin transistor, and therefore,the short channel effect of the carbon nanotube three-dimensional fin transistor can be reduced. In addition, according to the carbon nanotube three-dimensional fin transistor, the potential distribution in a channel can be affected by applying a voltage to an embedded metal gate fin, therefore, the discrete regulation of a device threshold can be achieved, and the function of dynamically controlling the threshold of the device is achieved.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and more specifically, relates to a carbon nanotube three-dimensional fin transistor and a preparation method thereof. Background technique [0002] Moore's Law means that when the price remains constant, the number of components that can be accommodated on an integrated circuit will double every 18-24 months, and the performance will also double. [0003] With the continuous shrinking of the size of semiconductor devices, it becomes more and more difficult for field effect transistors in traditional two-dimensional structure CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuits to continue Moore's Law. And with the advancement of Moore's Law and the shrinking of the size of logic devices, the short-channel effect is becoming more and more obvious, such as the increase of the sub-threshold swing and the decrease of the potenti...

AI Technical Summary

Problems solved by technology

[0003] With the continuous shrinking of the size of semiconductor devices, it is becoming more and more difficult for field effect transistors in traditional two-dimensional structure CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuits to continue Moore's Law

And with the advancement of Moore's law and the shrinking of the size of logic devices, the short-channel effect is becoming more and more obvious, such as the increase of sub-threshold swing and the decrease of the potential barrier caused by the drain, which all lead to the exponential off-state current of logic devices. level up

Images