Ion implantation method of P-type well, P-type well structure and CMOS device manufacturing method

Abstract

The invention relates to an ion implantation method of a P-type well, a P-type well structure and a CMOS device manufacturing method, and relates to the semiconductor integrated circuit manufacturingprocess. In the ion implantation process of the P-type well structure, the carbon ion implantation process is added between the well inhibition punch-through ion implantation process and the thresholdvoltage adjustment ion implantation process, so an amorphous layer of a carbon ion implantation layer is formed between an inhibition punch-through ion implantation layer and a threshold voltage adjustment ion implantation layer. The amorphous layer can inhibit ions of the inhibition punch-through ion implantation layer from diffusing to the threshold voltage adjustment ion implantation layer, the concentration of the shallowly-doped side of a PN junction is kept unchanged, and increase of parasitic capacitance of the PN junction is prevented.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to an ion implantation method of a P-type well, a P-type well structure and a CMOS device manufacturing method. Background technique [0002] With the rapid development of VLSI technology, the size of MOSFET devices such as channel length and gate oxide thickness is continuously reduced in proportion. The improvement of the performance of semiconductor devices in the future will face three challenges: 1. Device drain The increase of current, 2. The increase of source / drain resistance, 3. The mismatch of device parameters and the reduction of device manufacturing process debugging window. Among them, the rapidly increasing leakage current of the device is the main factor affecting the working performance of the device. [0003] figure 1 It is a schematic diagram of the generation of leakage current in semiconductor devices. The increase of leakage current ...

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Problems solved by technology

However, this traditional well structure will cause a large parasitic capacitance between the source and drain regions and the well, resulting in slower operating frequency of the device.

In order to reduce this parasitic capacitance, a high-energy and low-dose ion implantation process is generally used to form a graded junction between the source / drain and the well of the device during source and drain implantation to reduce the parasitic capacitance, but This step of ion implantation will cause the device to have a poor short channel effect and the high-energy ion implantation will break down the polysilicon (poly), resulting in a decrease in the threshold voltage of the device and increasing the leakage current of the device.

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