DLL locking indication circuit and method
A technology of locking indication and circuit, applied in the direction of electrical components, automatic power control, etc., can solve the problem of output clock phase deviation from the required clock phase, etc., and achieve the effect of stable and reliable work
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0035] The present invention provides a DLL lock indication circuit, its structure is as follows figure 1 As shown, it includes a phase detector module 11 , a charge pump / loop filter module 12 , a voltage-controlled delay line module 13 and a lock indication module 14 . Specifically, the phase detector module 11 compares the phase differences between the three input clock signals CLKD_0, CLKD_N, and CLKD_2N, and outputs pulse control signals UP, DN; the charge pump / loop filter module 12 according to the pulse Control signal UP, DN to control voltage V C charging and discharging; the voltage-controlled delay line module 13 controls the voltage V C Adjust its delay, and the delay is about the control voltage V C It has monotonicity and good linearity, and outputs a total of 2N clock signals CLKD_1~CLKD_2N; the lock indication module 14 determines whether the DLL is locked according to the 2N clock signals, and indicates whether it is correctly locked or incorrectly locked. In...
Embodiment 2
[0041] The present invention provides a DLL lock indication method, the schematic diagram is as follows figure 2 shown, including the following steps:
[0042] Step 1, the circuit system configures the buffer in the pulse generating unit to determine its delay;
[0043] Step 2, the circuit system configures the counter M to determine the number of times that the continuous sampling value required to pull the locking indicator high is high;
[0044] Step 3, DLL starts to work after reset, and generates narrow pulse CLK_PULSE whose width is determined by step 1;
[0045] Step 4, the clock signal CLKD_2N clock samples the narrow pulse CLK_PULSE, if it is high for M consecutive cycles, it is judged that the DLL is locked, and the lock indication signal is pulled high;
[0046] Step 5. When it is detected that the lock indication signal is high, the lock type judging unit starts to work, and the clock signals CLKD_1 to CLKD_(N-1) sample the clock signal CLKD_0;
[0047] Step 6....
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 

