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DLL locking indication circuit and method

A technology of locking indication and circuit, applied in the direction of electrical components, automatic power control, etc., can solve the problem of output clock phase deviation from the required clock phase, etc., and achieve the effect of stable and reliable work

Active Publication Date: 2020-02-11
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a DLL lock indication circuit and method to solve the current problem that DLL is prone to harmonic lock due to the large delay range covered by the voltage-controlled delay line, thus causing the output clock phase to deviate from the required clock phase.

Method used

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Embodiment 1

[0035] The present invention provides a DLL lock indication circuit, its structure is as follows figure 1 As shown, it includes a phase detector module 11 , a charge pump / loop filter module 12 , a voltage-controlled delay line module 13 and a lock indication module 14 . Specifically, the phase detector module 11 compares the phase differences between the three input clock signals CLKD_0, CLKD_N, and CLKD_2N, and outputs pulse control signals UP, DN; the charge pump / loop filter module 12 according to the pulse Control signal UP, DN to control voltage V C charging and discharging; the voltage-controlled delay line module 13 controls the voltage V C Adjust its delay, and the delay is about the control voltage V C It has monotonicity and good linearity, and outputs a total of 2N clock signals CLKD_1~CLKD_2N; the lock indication module 14 determines whether the DLL is locked according to the 2N clock signals, and indicates whether it is correctly locked or incorrectly locked. In...

Embodiment 2

[0041] The present invention provides a DLL lock indication method, the schematic diagram is as follows figure 2 shown, including the following steps:

[0042] Step 1, the circuit system configures the buffer in the pulse generating unit to determine its delay;

[0043] Step 2, the circuit system configures the counter M to determine the number of times that the continuous sampling value required to pull the locking indicator high is high;

[0044] Step 3, DLL starts to work after reset, and generates narrow pulse CLK_PULSE whose width is determined by step 1;

[0045] Step 4, the clock signal CLKD_2N clock samples the narrow pulse CLK_PULSE, if it is high for M consecutive cycles, it is judged that the DLL is locked, and the lock indication signal is pulled high;

[0046] Step 5. When it is detected that the lock indication signal is high, the lock type judging unit starts to work, and the clock signals CLKD_1 to CLKD_(N-1) sample the clock signal CLKD_0;

[0047] Step 6....

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Abstract

The invention discloses a DLL locking indication circuit and method, and belongs to the technical field of integrated circuit design. The DLL locking indication circuit comprises a phase discriminatormodule, a charge pump / loop filter module, a voltage-controlled delay line module and a locking indication module; the phase discriminator module compares phase differences among three input clocks ofCLKD _ 0, CLKD _ N and CLKD _ 2N and outputs pulse control signals UP and DN; the charge pump / loop filter module charges and discharges the control voltage VC according to the pulse control signals UP and DN; the voltage-controlled delay line module adjusts the delay of the voltage-controlled delay line module by controlling the voltage VC and outputs 2N clock signals from CLKD _ 1 to CLKD _ 2N;and the locking indication module judges whether the DLL is locked or not according to the 2N clock signals and indicates whether the DLL is locked correctly or harmonically.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a DLL lock indicating circuit and method. Background technique [0002] With the rapid development of integrated circuits, the operating speed of circuit systems is getting higher and higher, which poses challenges to data transmission and recovery. To reduce the need for high-speed clocks, multi-phase clocks become a solution. DLL (Delay-Locked Loop, delay-locked loop) can generate fixed-interval multi-phase clocks, which are widely used in data recovery, oversampling and other fields. As the clock frequency range becomes wider and wider, how to ensure that the DLL correctly locks and outputs multi-phase clocks at each frequency has become a key requirement for DLL design. [0003] DLL works in multiple frequency bands, and the voltage-controlled delay line needs to cover a large delay range. At this time, harmonic locking is prone to occur, that is, the over...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/095
CPCH03L7/095
Inventor 吴江
Owner 58TH RES INST OF CETC