Beam adjustment method hardware accelerator based on Zynq FPGA

A technology of beam adjustment and hardware accelerator, which is applied in the direction of instruments, digital computer components, and architecture with a single central processing unit, etc., can solve the problems of performance and power consumption affecting BA applications, etc., to reduce on-chip RAM consumption and improve The effect of parallelism

Active Publication Date: 2020-03-27
TIANJIN UNIV
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Problems solved by technology

[0004] But at present, whether it is in the local BA calculation of the robot in SLAM or in the offline SfM visua

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  • Beam adjustment method hardware accelerator based on Zynq FPGA
  • Beam adjustment method hardware accelerator based on Zynq FPGA
  • Beam adjustment method hardware accelerator based on Zynq FPGA

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Embodiment Construction

[0018] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0019] Such as figure 1 As shown, the present invention is based on the beam adjustment hardware accelerator of Zynq FPGA, the Schur elimination in the beam adjustment method, the Jacobian matrix update and the cost function calculation part are realized by circuit design at the PL end of Zynq, and other parts are implemented in Zynq The PS end is realized through software programming;

[0020] The PL side of the accelerator splits two hardware circuits according to the algorithm, Shure eliminates the use of separate hardware, and Jacobian matrix update and cost function calculation share the same hardware;

[0021] The internal circuits of the accelerator form different computing u...

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Abstract

The invention discloses a beam adjustment method hardware accelerator based on a Zynq FPGA. Shuer elimination, jacobian matrix updating and cost function calculation parts in a beam adjustment methodare realized at a PL end of Zynq through circuit design, and other parts are realized at a PS end of Zynq through software programming; an accelerator PL end splits two hardware circuits according toan algorithm, independent hardware is used for Shuer elimination, and Jacobian matrix updating and cost function calculation share the same hardware; wherein different computing units are formed in aninternal circuit of the accelerator, data transmission is carried out between the computing units by adopting a dual-port RAM (Random Access Memory) on an FPGA (Field Programmable Gate Array) chip, afinite-state machine is adopted in each computing unit, and read-in, read-out and storage of each step of data are controlled through state conversion; the Jacobian matrix updating and cost functioncalculating module calculates a Jacobian matrix by adopting a mode of combining analytic differential and automatic differential and calculates a cost function at the same time. BA calculation energyconsumption can be greatly reduced.

Description

technical field [0001] The invention relates to the technical field of hardware accelerators, in particular to a Zynq FPGA-based beam adjustment hardware accelerator. Background technique [0002] The bundle adjustment method (Bundle Adjustment, BA) obtains the optimal visual reconstruction effect by optimizing the camera parameters and the position of the three-dimensional space feature points at the same time. Optimum means to find the optimal parameter estimate by minimizing the quantization model, and simultaneous optimization of the two means that both the three-dimensional space feature points and the parameters of the camera are optimal. It is widely used in the reconstruction and simultaneous localization and mapping (SLAM) of 3D stereoscopic scenes. The goal of BA is to find optimal parameter estimates, i.e. point locations and camera parameters in 3D space, by minimizing the reprojection error. The error is defined as the L2 norm of the difference between the obs...

Claims

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Application Information

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IPC IPC(8): G06F9/448G06F15/78
CPCG06F9/4498G06F15/7896
Inventor 刘强秦书臻
Owner TIANJIN UNIV
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