Manufacturing method of lateral double-diffused transistor

Abstract

The invention relates to a manufacturing method of a lateral double-diffused transistor. The manufacturing method comprises the following steps that: a first liner oxide layer is formed on the surfaceof a substrate, and a P-type well region and an N-type well region which are separated from each other are formed on the substrate; an N-type drift region is formed in the substrate through the opening of a first hard mask, wherein the N-type drift region is spaced apart from the P-type well region and adjacent to the N-type well region; a second liner oxide layer is formed on the N-type drift region and the N-type well region via the opening of the first hard mask, wherein the second liner oxide layer has a thickness greater than that of the first liner oxide layer; and a field oxide layer is formed on the N-type drift region via the opening of a second hard mask, wherein the second hard mask blocks a portion of the second liner oxide, wherein the portion of the second liner oxide is adjacent to the P-type well region. According to the manufacturing method, the drift region and the second liner oxide layer are formed through the opening of the first hard mask, so that the thickness of the edge of the beak region of the field oxide layer is increased, and therefore, the electric field of the substrate below the beak region is reduced, and the breakdown voltage of the transistor iseffectively improved while process cost is saved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a method for manufacturing a lateral double-diffused transistor. Background technique [0002] As a type of power field effect transistor, laterally diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, etc. Excellent characteristics, so it has been widely used, and people have higher and higher performance requirements for LDMOS. [0003] In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory of. Generally speaking, the way to reduce ...

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Problems solved by technology

[0005] The existing manufacturing process reduces the concentration of the drift region or reduces the overlapping size of the drift region and the gate oxide layer. figure 1 The electric field at the star mark shown in the figure can increase the breakdown voltage, but this will increase the on-resistance of LDMOS, or increase the cost of process manufacturing

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