Simulation method, device and related equipment of pcie initialization process

Abstract

Embodiments of the present invention provide a simulation method, device and related equipment of a PCIe initialization process, which relate to the technical field of EDA simulation. The method controls the power-on of the pre-built PCIe simulation platform, releases the reset register by using the virtual processor, then uses the virtual processor to configure the acceleration simulation register according to the pre-stored assignment table, and uses the virtual processor to configure the accelerated simulation register according to the pre-stored function. After the information configures the PCIe physical layer register and the PCIe control register, the PCIe device is controlled to perform PCIe link training. The present invention shortens the simulation time for operations such as PLL locking and VCO calibration at the receiving end in the link training process by forcibly assigning values ​​to the acceleration emulation registers; at the same time, the present invention forcibly assigns values ​​to the acceleration emulation registers to ensure that the acceleration emulation registers are assigned values correctness, avoiding multiple iterations in the link training process, thereby shortening the simulation time of the entire PCI initialization process.

Description

technical field [0001] The invention relates to the technical field of EDA simulation, in particular to a simulation method, device and related equipment of a PCIe initialization process. Background technique [0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, which is widely used in personal computers, servers, Solid-state drives, data centers and other fields have been widely used. In the chip development process, Electronics Design Automation (EDA) simulation plays an important role in ensuring the functional integrity of the chip, solving real-time logistics (RTL) problems and netlist problems in chip development. Therefore, in the process of opening a PCIe device, EDA simulation is often used to verify related functions. [0003] However, in the prior art, after the initial power-on of the PCIePHY (Physical, physical layer), it is necessary to perform phase-locked loop (Phase Locked Loop, PLL) locking, volt...

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Problems solved by technology

[0003] However, in the prior art, after the initial power-on of the PCIePHY (Physical, physical layer), it is necessary to perform phase-locked loop (Phase Locked Loop, PLL) locking, voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) calibration at the receiving end, Receiver / transmitter detection, receiver analog front end (Analog Front End, AFE) / decision feedback equalization (Decision Feedback Equalization, DFE) calibration, etc., and the simulation time of these processes will take a long time, even up to several days, which is relatively consuming Time

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