Methods and apparatus for controlling warpage in wafer level packaging processes

Abstract

The invention discloses methods and apparatus for controlling warpage in wafer level packaging processes. Methods and apparatus for producing fine pitch patterning on a substrate are disclosed. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2 / 2 [mu]m l / s fine pitch patterning.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 751,200, filed October 26, 2018, which is incorporated herein by reference in its entirety. technical field [0003] Embodiments of the present principles relate generally to semiconductor processes for packaging semiconductor devices. Background technique [0004] Semiconductor wafers are processed to form structures on the surface of the wafer. Structures on specific areas of the wafer can be linked together to form microcircuits. A wafer may have many different microcircuits built up on the surface of the wafer during processing. Once wafer processing has been completed, the wafer is diced or diced to separate the microcircuits into semiconductor "chips." Chips often contain complex circuitry that requires interaction with external components. The internal circuitry of the chip is too small to connect directly to external co...

AI Technical Summary

Problems solved by technology

Warpage hinders the ability to form fine-pitch RDL layers on the wafer, greatly reducing yield

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