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MAC transmitting end, MAC receiving end and circuit, FPGA chip and data transmission system

A technology of transmitter and receiver, applied in the field of high-speed 1553 mixed service data framing circuit, can solve the problems of reduced communication reliability and low data transmission efficiency, and achieve the effect of reducing the bit error rate

Active Publication Date: 2020-05-29
西安云维智联科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003]1553 communication is a wired communication using a wireless communication algorithm. In the case of high-speed communication, the requirements for the frame length of the data are higher, and the longer the payload length of the frame is , the lower the data transmission efficiency and the lower the communication reliability

Method used

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  • MAC transmitting end, MAC receiving end and circuit, FPGA chip and data transmission system
  • MAC transmitting end, MAC receiving end and circuit, FPGA chip and data transmission system
  • MAC transmitting end, MAC receiving end and circuit, FPGA chip and data transmission system

Examples

Experimental program
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Embodiment 1

[0067] figure 1 For the entire data transmission system architecture, including multiple components of the MAC layer, PHY layer, PCI control layer and control signal processing layer.

[0068] The PHY layer acts as a link between the MAC layer and the IO interface, performs OFDM algorithm processing on the data processed by the MAC layer, and transmits data of different channels according to different frequency bandwidths. The single-channel baseband signal occupies a 5Mhz bandwidth, and every There is a guard interval between the frequency bandwidths of one channel, so that the data of each channel can be separated independently, so as to achieve mutual non-interference. Data restoration is performed on the data input by the IO port, and the received wireless data stream is down-converted and down-sampled to obtain all eight self-channel data. Tether data for eight sub-channels is independently signal detected, demodulated and decoded. The bits obtained by demodulation and ...

Embodiment 2

[0072] Example 2:

[0073] In this embodiment, a MAC transmitting end and a MAC receiving end are taken as examples to describe the MAC layer.

[0074] The main circuit of the MAC layer transmitter or transmitter circuit includes the data frame storage and frame sealing module of the transmitter, the channel buffer module, and the data transmission module. The MAC layer receiver or receiver circuit includes the data receiver module of the receiver, the channel buffer module, and the data frame Frame storage modules.

[0075] The transmitting end or transmitting end circuit of the MAC layer mainly implements user frame slicing and sealing: the main realization depends on:

[0076] The storage and framing module caches the user frames sent by the upper-layer client, converts 32-bit wide data into 8-bit wide data and crosses the clock domain, and slices the user frames into multiple logical frames according to different frame types. Data frame, and the logical data frame is seq...

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Abstract

The invention discloses an MAC transmitting end, an MAC receiving end and circuit, an FPGA chip and a data transmission system. The MAC transmitting end is executed according to the following steps: caching a user frame issued by an upper layer, sealing the cached user frame into logic frames of a first frame, a plurality of intermediate frames and a tail frame according to frame header information of the user frame, marking the first frame and the tail frame during frame sealing, writing the logic frames into a cache channel of the transmitting end in sequence, and reading out and transmitting the logic frames in the cache channel of the transmitting end. The MAC receiving end is executed according to the following steps: receiving the logic frames, writing the received logic frames intoa receiving end cache channel, wherein the configuration of the receiving end cache channel corresponds to the configuration of the transmitting end cache channel, identifying the logic frames in thecache channel of the receiving end to determine a first frame, taking a frame header of the first frame as a frame header of a user frame, taking a frame load of the first frame, a frame load of a middle frame and a frame load of the tail frame as frame loads of the user frame for framing, and restoring the user frame. The whole data transmission system disclosed by the invention can perform 100M-rate transmission and is low in bit error rate.

Description

technical field [0001] The invention relates to the field of 1553 data information transmission, in particular to an FPGA-based high-speed 1553 mixed service data frame sealing and framing circuit and an information data processing method. Background technique [0002] The 1553b bus is an information transmission bus standard developed by the US military for equipment on aircraft, that is, a protocol for transmission between devices. The traditional 1553 standard has been widely used in backbone communications with military purposes such as aviation, aerospace, and weapons since it was proposed in the 1970s. [0003] 1553 communication is a wired communication using a wireless communication algorithm. In the case of high-speed communication, the requirements for the frame length of the data are relatively high. The longer the payload length of the frame, the lower the data transmission efficiency and the lower the communication reliability. . In traditional data communicat...

Claims

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Application Information

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IPC IPC(8): H04L1/00H04L1/20
CPCH04L1/0007H04L1/0083H04L1/201H04L1/203
Inventor 王红春赵多王国栋刘晓平
Owner 西安云维智联科技有限公司
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