Electrostatic discharge protection structure and electrostatic discharge protection circuit

Abstract

The invention relates to an electrostatic discharge protection structure and an electrostatic discharge protection circuit, and the structure comprises a substrate which is provided with two drift regions which are arranged in parallel and are isolated from each other; an LDMOS transistor which is located in each drift region and comprises a gate structure, a body region located in the drift region on one side of the gate structure, a source region and a drain region, wherein the source region and the drain region are located on the two sides of the gate structure, and the gate structure stretches across the interface surface of the drift region and the body region; the source regions in the two drift regions are connected; the gate structures are connected with the corresponding source regions; the body region is connected with the peripheral frequency detection circuit, and the peripheral frequency detection circuit pulls up the potential of the body region when detecting an electrostatic discharge signal; and the drain region in one drift region is connected with the electrostatic discharge input end, and the drain region in the other drift region is connected with the groundingend. According to the embodiment of the invention, the problem that the current of the negative voltage signal flows backwards in the electrostatic discharge protection structure when the chip protected by the electrostatic discharge protection structure works normally is avoided, and the electrostatic discharge protection capability of the electrostatic discharge protection structure is improved.

Description

technical field [0001] The embodiments of the present invention relate to the field of electrostatic discharge protection, in particular to an electrostatic discharge protection structure and an electrostatic discharge protection circuit. Background technique [0002] Electrostatic discharge is a common phenomenon in the process of manufacturing, producing, assembling, testing, storing, and transporting semiconductor devices or circuits. The / output pin is passed into the integrated circuit and destroys the internal circuit of the integrated circuit. [0003] In order to solve this problem, it is usually necessary to set up a protection circuit between the internal circuit and the input / output pin. This protection circuit must be activated before the pulse current of electrostatic discharge reaches the internal circuit to quickly eliminate the excessive voltage. Further, damage caused by ESD (Electrostatic Discharge, electrostatic discharge) phenomenon is reduced. [0004]...

AI Technical Summary

Problems solved by technology

[0004] Power management IC (Integrated Circuit, integrated circuit), driver IC and automatic IC play an important role in daily applications, and high-voltage ESD protection is becoming more and more important for these IC devices, but these high-voltage IC devices are due to their inherent electrostatic stress tolerance Weak resulting in poor ESD robustness

Moreover, when the voltage connected to the input / output pins of the power management IC (integrated circuit), driver IC, and automatic IC is negative, the parasitic diode in the electrostatic discharge protection structure conducts forward, and the signal cannot be input or output to inside / outside the chip, thus disabling the chip

[0005] In addition, the high-voltage pins in the IC are also sensitive to the latch-up effect. When the IC is powered for a stress ESD test, if the maintenance voltage of the ESD clamping protection device is lower than the supply voltage, after the ESD test is completed, the ESD clamping component will be open all the time, which will cause a large current and damage the high voltage IC device

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