Preparation method of rewiring layer and semiconductor structure

Abstract

The invention provides a preparation method of a rewiring layer and a semiconductor structure. The semiconductor structure comprises a substrate and the rewiring layer located on the upper surface ofthe substrate. The rewiring layer comprises a metal column; a dielectric layer, wherein the dielectric layer wraps the metal column, and the dielectric layer comprises a trench, the width of the trench being smaller than that of the metal column, and the upper surface of the metal column being exposed through the trench; a metal seed layer, which covers the upper surface of the dielectric layer and the bottom and the side wall of the trench; and a metal layer which fills the trench and covers the metal seed layer on the dielectric layer. According to the invention, the depth-to-width ratio oftrench filling in the dielectric layer is reduced by manufacturing the early-stage metal columns, and then the metal layer is manufactured, so that the flatness of the rewiring layer can be improved,grooves are prevented from being generated in the formed rewiring layer, the subsequent manufacturing process is facilitated, the process risk of multilayer stacking is reduced, and the process difficulty and cost are reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and relates to a preparation method of a rewiring layer and a semiconductor structure. Background technique [0002] With the increasingly powerful functions, higher performance and integration of integrated circuits, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density. [0003] Due to the advantages of miniaturization, low cost, high integration, better performance and higher energy efficiency, wafer-level packaging (WLP) technology has become an important part of electronic equipment such as demanding mo...

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for preparing a rewiring layer and a semiconductor structure, which are used to solve the problems of complex, time-consuming, and high-cost preparation of RDL in the prior art, and The above-mentioned series of process problems caused by the deep grooves in the prepared RDL

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