Lateral double-diffused transistor and manufacturing method thereof

Abstract

The invention discloses a lateral double-diffused transistor and a manufacturing method thereof. The lateral double-diffused transistor comprises: a substrate; a drift region located at the top of thesubstrate; a drain region and a body region respectively positioned on two opposite sides of the top of the drift region; a source region and a body contact region positioned in the body region and adjacent to each other; and a dielectric layer and a field plate layer sequentially stacked on the surface of the drift region, wherein the body region partially extends towards the direction of the drain region to form at least one body region extending region, the body region extending region and the drift region adjacent to the body region extending region are distributed in an interdigitated manner, the body contact region is located on the side, away from the drain region, in the body region, and the body contact region partially extends in the direction where the drain region is located to form a body contact region extending region. According to the lateral double-diffused transistor, the interdigital body region and the sawtooth-shaped body contact region are arranged, so that the channel density of the device is increased, the on resistance is reduced, the body region resistance can be effectively reduced, and parasitic NPN false opening is prevented.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a lateral double-diffused transistor and a manufacturing method thereof. Background technique [0002] As a type of power field effect transistor, lateral double-diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance and other excellent properties, so it has been widely used. In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory However, it is difficult to reduce the on-resistance and increase the breakdown voltage at the same time. [...

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Problems solved by technology

In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory However, it is difficult to reduce the on-resistance and increase the breakdown voltage at the same time

[0003] LDMOS devices are usually used in the case of high current and high voltage. When the device is turned on, a large hole current flows from the body region to the body contact region, and the potential of the body region will be raised, which may cause Causes the parasitic NPN (N+ source-P-type body region-N-type drift region) to be turned on by mistake, and the device fails functionally

The greater the operating current of the device, the easier it is for the parasitic NPN to be turned on by mistake. Therefore, at present, LDMOS often fails when used in the case of high current and high voltage.

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