Lateral double diffused transistor and manufacturing method thereof

Abstract

Disclosed is a lateral double-diffusion transistor and a manufacturing method thereof, the lateral double-diffusion transistor includes a substrate; a drift region located on the top of the substrate; a drain region and a body region respectively located on opposite sides of the top of the drift region; The source region and the body contact region are located inside the body region and are adjacent to each other; and the dielectric layer and the field plate layer are sequentially stacked on the surface of the drift region; the body region part faces the direction of the drain region extended to form at least one body region extension region, the body region extension region and the drift region adjacent to it are interdigitated; the body contact region is located on the side of the body region away from the drain region , and part of the body contact region extends toward the direction where the drain region is located, forming a body contact region extension region. The lateral double-diffusion crystal interdigitated body region and the zigzag body contact region increase the channel density of the device, reduce the on-resistance, and effectively reduce the resistance of the body region, preventing parasitic NPN from turning on by mistake.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a lateral double-diffused transistor and a manufacturing method thereof. Background technique [0002] As a type of power field effect transistor, lateral double-diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance and other excellent properties, so it has been widely used. In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory However, it is difficult to reduce the on-resistance and increase the breakdown voltage at the same time. [...

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Problems solved by technology

In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory However, it is difficult to reduce the on-resistance and increase the breakdown voltage at the same time

[0003] LDMOS devices are usually used in the case of high current and high voltage. When the device is turned on, a large hole current flows from the body region to the body contact region, and the potential of the body region will be raised, which may cause Causes the parasitic NPN (N+ source-P-type body region-N-type drift region) to be turned on by mistake, and the device fails functionally

The greater the operating current of the device, the easier it is for the parasitic NPN to be turned on by mistake. Therefore, at present, LDMOS often fails when used in the case of high current and high voltage.

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