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Semiconductor structure

A semiconductor and capacitor structure technology, applied in transistors and other directions, can solve the problems of slow production speed and long production cycle, and achieve the effect of improving production speed and density

Pending Publication Date: 2020-10-09
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In addition, when using planar technology and manufacturing technology to make memory chips such as DRAM, due to the limitation of the process sequence, the production cycle is longer and the production speed is slower.

Method used

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  • Semiconductor structure
  • Semiconductor structure
  • Semiconductor structure

Examples

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Embodiment Construction

[0052]Example embodiments will now be described more fully with reference to the accompanying drawings. Exemplary embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these examples are provided so that this disclosure will be thorough and complete and will fully convey the concept of the exemplary embodiments communicated to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0053] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the description in the accompanying drawings directions for the example described above. It will be appreciated that if the modules of the icon are...

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Abstract

The invention provides a semiconductor structure, and relates to the technical field of semiconductor production. The structure comprises a first wafer and a second wafer which are stacked into a whole, wherein the first wafer comprises a capacitance area and a non-capacitance area; the second wafer comprises an array region and a control region; the capacitor region corresponds to the array region, and the non-capacitor region corresponds to the control region; and the first wafer is electrically connected with the second wafer. According to the technical scheme provided by the invention, thesemiconductor structure is formed by stacking the two wafers, and compared with the prior art, the structure can improve the density and the production speed of the semiconductor structure on the wafers.

Description

technical field [0001] The invention relates to the technical field of semiconductor production, in particular to a semiconductor structure. Background technique [0002] DRAM (Dynamic Random Access Memory, dynamic random access memory) and other memory chips and other semiconductor devices are mostly planar structures. By improving process technology, circuit design, programming algorithms and manufacturing processes, semiconductor devices can be scaled to smaller sizes . However, as the feature size of semiconductor devices approaches the lower limit, planar processes and fabrication techniques become challenging and costly. [0003] With the miniaturization and thinning of electronic devices and memories, there are higher requirements for the volume and thickness of memory chips. [0004] In addition, when using planar technology and manufacturing technology to manufacture memory chips such as DRAM, due to the limitation of the process sequence, the production cycle is ...

Claims

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Application Information

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IPC IPC(8): H01L27/108
CPCH10B12/00
Inventor 朱一明平尔萱
Owner CHANGXIN MEMORY TECH INC
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