Chip and forming method thereof

Abstract

The invention provides a chip and a method of forming the same. The chip includes: a substrate including a storage region and a peripheral region; a storage array formed in the storage region; at least one anti-fuse device formed in the peripheral region and used for repairing a storage defect caused by a failure storage unit in the storage array, wherein the anti-fuse device comprises a gate structure located on the surface of the substrate, and the gate structure comprises a gate dielectric layer located on the surface of the substrate and a gate located on the surface of the gate dielectriclayer; and a doped region arranged in the substrate on one side of the gate structure parallel to the surface direction of the substrate, wherein at least part of the edge of the doped region is aligned with the edge of the gate or is positioned below the gate, and the anti-fuse device is easier to be broken down.

Description

technical field [0001] The invention relates to the field of storage technology, in particular to a chip and a forming method thereof. Background technique [0002] DRAM chips manufactured by semiconductor manufacturing process will inevitably produce defective memory cells, and redundant memory cells are usually formed on the DRAM chip, and the redundant memory cells can be used to permanently replace the defective memory cells to repair the DRAM chip. [0003] When repairing a DRAM chip, one time programming (OTP, one timeprogram) devices such as fuses or antifuses are needed. With the reduction of the feature size of the semiconductor process, the thickness of the gate dielectric layer of the MOS transistor structure is very thin, so that the MOS structure can be used as an anti-fuse device. [0004] In the prior art, the formation process of the anti-fuse device is relatively complicated, and the resistance in the breakdown process is relatively large, so it is difficul...

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Problems solved by technology

[0004] In the prior art, the formation process of the anti-fuse device is relatively complicated, and the resistance during the breakdown process is relatively large, so it is difficult to achieve a large breakdown current, which affects the repair efficiency of the chip

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