Separated gate VDMOS device with high reliability and manufacturing method thereof
A separated gate and reliability technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting device withstand voltage, insufficient transition region depletion, etc., to eliminate breakdown and reduce the transition region area , to avoid the effect of electric field concentration
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0040] Such as image 3 and Figure 4 As shown, it is a schematic structural diagram of a highly reliable split-gate VDMOS device according to Embodiment 1 of the present invention, including:
[0041] heavily doped first conductivity type substrate 11, first conductivity type drift region 12, first dielectric oxide layer 31, separation gate polycrystalline electrode 41, second dielectric oxide layer 32, third dielectric oxide layer 33, control gate polycrystalline Crystal electrode 42, second conductivity type well region 21, heavily doped first conductivity type region 13, heavily doped second conductivity type region 22, source metal contact 51, control gate metal contact 52, separation gate metal contact 53, the fourth dielectric oxide layer 34;
[0042] In the cell region, the first dielectric oxide layer 31, the second dielectric oxide layer 32, the third dielectric oxide layer 33 and the fourth dielectric oxide layer 34, the separation gate polycrystalline electrode 4...
Embodiment 2
[0060] Such as Figure 5 As shown, it is a top view of the high-reliability split-gate VDMOS device of Example 2 of the present invention. Compared with Example 1, the difference is that the heavily doped first conductivity type region 13 is directly implanted without using a mask. form. The groove structures in the two embodiments 1 with opposite directions appear periodically and alternately in the heavily doped first conductivity type region 13, so that the groove width of the device cell region and the groove width of the terminal region are independent, and the groove width of the cell region can be as large as possible. The narrowing does not affect the extraction of the transition region from the gate, and the rest of the working principle is basically the same as that of Embodiment 1.
Embodiment 3
[0062] Such as Figure 6 As shown, it is a top view of the high-reliability split-gate VDMOS device of Embodiment 3 of the present invention. Compared with Embodiment 2, the difference is that the transition region structure described in Embodiment 1 is located in the middle of the entire device and the groove structure , and the upper and lower ends of the transition region structure are connected to the cell region groove structure, and the control gate metal contact 52 is located at the two ends of the cell region groove structure near the terminal, and the two control gate metal contacts 52 increase the control ability of the control gate , the rest of the working principles are basically the same as in Embodiment 1.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More - R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com



