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Wafer cutting method

A cutting method and wafer technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to achieve the effect of improving edge chipping and improving yield

Inactive Publication Date: 2020-12-22
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] As the size of the chip becomes smaller, the width of the scribe area is also gradually reduced, and the reduction of the width of the scribe area also brings severe challenges to the die saw process.

Method used

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Embodiment Construction

[0032] Silicon on insulator (SOI) technology can effectively resist transient radiation and single event radiation due to its full dielectric isolation structure, so it is the preferred technology for manufacturing radiation-hardened integrated circuits. Devices based on SOI substrates have the advantages of high speed, low operating voltage, low power consumption, and high temperature resistance. Therefore, SOI technology has great application prospects in submicron VLSI.

[0033] However, when a wafer formed based on the SOI technology is diced, the yield rate of chips obtained after dicing is low. The reason is analyzed in conjunction with a wafer cutting method.

[0034] Figure 1 to Figure 2 It is a structural schematic diagram corresponding to each step in a wafer cutting method.

[0035] refer to figure 1 , to obtain a wafer 10 to be diced, including an isolation layer 11 and a semiconductor device layer 12 on the isolation layer 11, the wafer 10 to be diced includes...

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Abstract

A wafer cutting method comprises the steps of: obtaining a wafer to be cut, wherein the wafer to be cut comprises an isolation layer and a semiconductor device layer located on the isolation layer, and the wafer to be cut comprises a cutting channel area; performing first cutting on the isolation layer in the cutting channel area from one side, back to the semiconductor device layer, of the isolation layer to form a first cutting groove penetrating through the isolation layer; and performing second cutting on the semiconductor device layer at the position of the first cutting groove from one side, back to the isolation layer, of the semiconductor device layer to form a cutting channel penetrating through the wafer to be cut, and obtaining a plurality of discrete chips. When first cutting is carried out, the semiconductor device layer can provide supporting force for the isolation layer, so that the transverse size of the edge breakage opening in the position of the first cutting grooveis reduced, correspondingly, after second cutting is completed, the transverse size of the edge breakage opening in the position of the cutting channel is also small, and therefore the yield of chipsobtained after cutting is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a wafer cutting method. Background technique [0002] Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Various circuit element structures can be processed on the silicon wafer to become integrated circuit (integrated circuit, IC) devices with specific electrical functions. After the preparation of the semiconductor wafer is completed, the chip needs to be diced to divide the semiconductor wafer into a plurality of chips, wherein the dicing process is performed in the dicing line area. [0003] The current wafer dicing method mainly includes: firstly performing backside grinding on the back of the wafer, and then using a dicing blade to cut from the front of the wafer to the back of the wafer along the dicing line area to obtain multiple independent wafers. chip. Among them, the front side...

Claims

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Application Information

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IPC IPC(8): H01L21/304H01L21/78
CPCH01L21/3043H01L21/78
Inventor 宋月平
Owner NINGBO SEMICON INT CORP