Bit line driving structure and three-dimensional memory structure

Abstract

The invention provides a bit line driving structure and a three-dimensional memory structure. The bit line driving structure comprises: a first substrate; and a driving device array which is formed onone side of the first surface of the first substrate and is formed by arranging a plurality of driving devices, wherein the driving device comprises an active device region, a source region, a drainregion and a gate structure, the source region and the drain region are respectively positioned on two sides of the gate structure, gaps are formed among the active device regions, in the same row ofdriving devices arranged in the row direction, the widths of the source region and the drain region of the driving devices located on the edges of the two sides are larger than those of the source region and the drain region of the driving devices located on the edges of the non-two sides. According to the invention, a driving device with wider source and drain region widths in edge regions on twosides in the row direction is introduced, and the source and drain breakdown voltage of the device is improved by increasing the source and drain region widths in the edge regions, increasing the junction area of the device, broadening a depletion region and reducing an electric field; and by improving the weak point of voltage withstanding of the driving device array, the overall voltage withstanding performance of the driving device array is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a bit line driving structure and a three-dimensional memory structure. Background technique [0002] As the capacity and number of layers of 3D NAND memory continue to increase, the operating voltage used to drive the memory also increases, and related circuits need to ensure that they work under higher voltage conditions without breakdown and other abnormalities. For example, in the erasing operation of some memory cells, the bit line driver circuit needs to withstand a high voltage of at least 23V, and as the device design requires that the threshold voltage distribution of array cells be more convergent, the voltage value will be further increased. [0003] Currently, corresponding to the array structure of memory strings in 3D NAND, the peripheral bit line driving circuits also have an array structure, and are connected to the bit lines of the mem...

AI Technical Summary

Problems solved by technology

Compared with the driving device located in the middle of the array with other driving devices on the left and right sides, the withstand voltage value of the driving device located at the edge of the array will drop significantly, making it the most likely to occur in the entire driving circuit array. Breakdown of Weak Links

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