3D NAND memory device and manufacturing method thereof

Abstract

The invention provides a 3D NAND memory device and a manufacturing method thereof. The method comprises the steps of after a step structure is formed, at least forming a step covering layer on the step structure, then at least forming a filling layer on the step covering layer, wherein the step covering layer is made of a material capable of preventing free radicals in the filling layer from diffusing to a stacking layer, so that a barrier layer of free radicals can be formed between the filling layer and the step structure, and even if free radicals of H roots and OH roots exist in the filling layer, the released free radicals of the H roots and OH roots can be blocked by the step covering layer and cannot diffuse into the step structure, and accordingly the step structure cannot be eroded, the step structure is protected, and the device performance is improved.

Description

[0001] This application is a divisional application of the invention patent application with application number 201910198433.5 submitted on March 15, 2019. technical field [0002] The invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a 3D NAND storage device and a manufacturing method thereof. Background technique [0003] NAND storage devices are non-volatile storage products with low power consumption, fast read and write speed and large capacity, and are widely used in electronic products. [0004] Planar NAND devices are close to the limit of practical expansion. In order to further increase storage capacity and reduce storage cost per bit, 3D NAND storage devices are proposed. In the structure of 3D NAND storage devices, a method of vertically stacking multi-layer gates and inter-gate insulating layers is adopted. The central area of ​​the stacked layers is the core storage area, and the edge area is a stepped structure...

AI Technical Summary

Problems solved by technology

[0005] In the manufacturing process of 3D NAND storage devices, after the step structure is formed, a dielectric material layer is filled on the step structure. The formation process of the dielectric material layer is a process with good filling capacity, and the silicon oxide formed by these processes is rich in hydrogen radicals ( h + ) and hydroxide (OH - ) free radicals, during the subsequent thermal annealing process, these free radicals release (Out-gas), which will cause erosion to the step structure, especially the gate or the sacrificial layer at the gate position, in addition, the incompletely released free radicals It may also be further released during the subsequent deposition of a carbon-containing hard mask to cause arcing, which may cause machine alarms in the slightest, and cause film peeling, peeling, or even fragments in severe cases, thereby affecting the yield rate.

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