Vertical transistor, memory and preparation method
A transistor and vertical technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that it is difficult to realize device miniaturization and high reliability at the same time, so as to improve the dielectric constant and enhance the gate control ability Effect
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Embodiment 1
[0089] refer to figure 1 , the present embodiment provides a method for fabricating a vertical transistor, comprising the following steps:
[0090] provide the basis;
[0091] forming a vertical transistor stack structure on the substrate;
[0092] patterning the transistor stack structure to expose part of the substrate;
[0093] forming an isolation layer on the substrate and the transistor stack structure;
[0094] Forming a ring gate structure, the ring gate structure includes a gate dielectric layer and a gate conductive layer, and the gate dielectric layer includes a first gate dielectric layer in contact with the transistor stack structure and a first gate dielectric layer in contact with the gate conductive layer a second gate dielectric layer in contact;
[0095] removing the second gate dielectric layer, forming a groove between the gate conductive layer and the first gate dielectric layer;
[0096] forming an ice dielectric layer in the groove;
[0097] formin...
Embodiment 2
[0138] refer to Figure 16 ~ Figure 18 , this embodiment also provides a vertical transistor, wherein the method for forming the vertical transistor can refer to the above-mentioned manufacturing method, but it is not limited thereto, and will not be repeated here.
[0139] The vertical transistor in this embodiment includes a substrate 100 , a transistor stack structure 200 , a gate-around structure, a passivation layer 900 and a metal connection portion 130 .
[0140] Wherein, the transistor stack structure 200 is located on the substrate 100; the ring gate structure includes a gate dielectric layer and a gate conductive layer 600, and the gate dielectric layer includes a The first gate dielectric layer 501 and the water dielectric layer 801 between the gate conductive layer 600 and the first gate dielectric layer 501; the passivation layer 900 covers the ring gate structure and transistor stack Structure 200 ; the metal connection part 130 is located in the passivation lay...
Embodiment 3
[0152] This embodiment also provides a method for manufacturing a vertical memory device. The method for manufacturing a vertical memory device includes using the method for manufacturing a vertical transistor in Embodiment 1 to prepare the memory device. Wherein, the formed vertical memory may include a 1T1C non-volatile memory structure, such as DRAM, and the specific type and preparation method of the vertical memory are not overly limited here.
[0153] In this embodiment, since the formed vertical memory is the vertical transistor with the water dielectric layer, the gate dielectric can be improved based on the water dielectric layer having a higher dielectric constant. The dielectric constant of the layer is used to enhance the gate control capability, so that the miniaturization and high reliability of the device can be realized at the same time.
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