Band-gap reference circuit and low-offset high-power-supply-rejection-ratio band-gap reference source
A reference circuit and reference technology, applied in the direction of regulating electrical variables, control/regulating systems, instruments, etc., can solve the problems affecting the accuracy of the reference voltage, the accuracy of the mirror current, and the accuracy of the reference, and achieve the increase and decrease of the power supply rejection ratio. Small channel modulation effect, reducing circuit mismatch effect
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Embodiment 1
[0061] see Figure 4 , the embodiment provides a bandgap reference circuit, comprising:
[0062] The sixteenth MOS transistor M16, the gate terminal of which is connected to the fifth reference point E, the current input terminal is connected to the high level VDD, and the current output terminal is connected to the current input terminal of the seventeenth MOS transistor M17;
[0063] The seventeenth MOS transistor M17, the gate terminal of which is connected to the fourth reference point D, and the current output terminal is connected to the reference output terminal VREF;
[0064] The third triode Q3, its current input terminal is connected to the reference output terminal VREF, the current output terminal is grounded, the base is connected to the sixth reference point F, and the base is connected to the current input terminal through a capacitor;
[0065] The second triode Q2, its current input terminal is connected to the reference output terminal VREF through the second...
Embodiment 2
[0068] Example 2: see Figure 4 .
[0069] This embodiment provides a bandgap reference source with low offset and high power supply rejection ratio, including a bandgap reference circuit, a bias circuit, a start-up circuit and a current comparator;
[0070] The bandgap reference circuit adopts the bandgap reference circuit described in Embodiment 1.
[0071] The bias circuit includes:
[0072] No. 0 MOS tube M0, its current input terminal (source terminal) is connected to high level VDD, and the gate terminal is connected to the fourth reference point D;
[0073] The first MOS transistor M1, its current input terminal (source terminal) is connected to the current output terminal (drain terminal) of the zero MOS transistor M0, and the gate terminal is connected to the fourth reference point D;
[0074] The second MOS transistor M3, its current input terminal (source terminal) is connected to a high level, and the gate terminal is connected to the fifth reference point;
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