Semiconductor structure and method of forming the same

Abstract

The present application discloses a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a plurality of storage areas, wherein the plurality of storage areas are arranged in an array on the substrate to form a storage device; and a plurality of scribe lines , each of the dicing lanes is located between two adjacent storage areas; alignment marks, located in the dicing lanes, are formed on the substrate, close to the center of the two storage areas; photolithography Glue, over the storage area and the scribe line, covers the alignment marks. The alignment mark is set at a position close to the middle of the two adjacent storage areas, and the photoresist above the position is relatively flat, so that the intensity of the measurement signal of the alignment mark measured through the photoresist is higher, and the The engraving accuracy is improved, the measurement error is small, the wafer pass rate is high, and the cost is reduced.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background technique [0002] As the feature sizes of semiconductor manufacturing processes are getting smaller and smaller, the storage density of memory devices is getting higher and higher. In order to further increase the storage density, three-dimensionally structured storage devices (ie, 3D storage devices) have been developed. 3D memory devices include multiple memory cells stacked in a vertical direction, which can exponentially increase the level of integration on a wafer per unit area, and can reduce costs. [0003] At present, 3D memory devices are stacked with more and more memory cells, corresponding to more and more semiconductor layers, and the height of the semiconductor structures formed on the wafer is getting higher and higher, and the step height of the effective...

AI Technical Summary

Problems solved by technology

The height difference between the 3D storage device and its surrounding dicing lines is more obvious. The higher the number of layers of the storage device near the dicing line, the higher the height of the photoresist layer on it, and the photoresist layer above the alignment mark in the dicing line Therefore, the profile of the photoresist layer above the alignment mark is uneven, which affects the strength and integrity of the test signal of the alignment mark, and the marking of the wafer is not accurate, resulting in a large Measurement errors lead to poor overlay accuracy (overlay, OVL), lower wafer pass rate; and, when the test signal is weak, the wafer may be misjudged as a non-qualified wafer, resulting in waste

[0004] In the prior art, the flatness of the photoresist is improved by slowing down the spin coating speed of the photoresist, but the effect is still unsatisfactory. After slowing down the spin coating speed, the wafer WPH (wafer per hour, output rate per hour) decreases ; and there is still residual (residual overlay performance indicator, ROPI) overlay error after correction

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