Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate; a plurality of storage areas which are arranged on the substrate in an array manner and are used for forming a storage device; a plurality of cutting channels, wherein each cutting channel is located between two adjacent storage areas; an alignment mark which is positioned in the cutting channel, is formed on the substrate and is close to the central position of the two storage areas; and a photoresist which is positioned above the storage area and the cutting channel and covers the alignment mark. The alignment mark is arranged at the position close to the middle of the two adjacent storage areas, and the photoresist above the position is relatively flat, so that the intensity of a measurement signal of the alignment mark measured by penetrating through the photoresist is relatively high, the overlay precision is improved, the measurement error is small, the wafer qualification rate is high, and the cost is reduced.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background technique [0002] As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] At present, more and more memory cells are stacked in 3D memory devices, corresponding to more and more semiconductor layers, the height of the semiconductor structure formed on the wafer is getting higher and higher, and the step height of the effective area of ​​the memory dev...

AI Technical Summary

Problems solved by technology

The height difference between the 3D storage device and its surrounding dicing lines is more obvious. The higher the number of layers of the storage device near the dicing line, the higher the height of the photoresist layer on it, and the photoresist layer above the alignment mark in the dicing line Therefore, the profile of the photoresist layer above the alignment mark is uneven, which affects the strength and integrity of the test signal of the alignment mark, and the marking of the wafer is not accurate, resulting in a large Measurement errors lead to poor overlay accuracy (overlay, OVL), lower wafer pass rate; and, when the test signal is weak, the wafer may be misjudged as a non-qualified wafer, resulting in waste

[0004] In the prior art, the flatness of the photoresist is improved by slowing down the spin coating speed of the photoresist, but the effect is still unsatisfactory. After slowing down the spin coating speed, the wafer WPH (wafer per hour, output rate per hour) decreases ; and there is still residual (residual overlay performance indicator, ROPI) overlay error after correction

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