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System-level packaging method and packaging structure

A system-level packaging and PCB board technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of large thickness and incompatible with the thinning of portable products, and reduce the bonding stress , Enhance the efficiency of electrical connection and simplify the packaging process

Inactive Publication Date: 2021-10-22
芯知微(上海)电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing system-in-package module integrates electronic components such as control chips, resistors, and inductors on the surface of the substrate, and the inductor is placed above the chip. In terms of thickness, the thickness of the system-in-package is relatively large, which is not suitable for portability. The characteristics of thinness emphasized by type products

Method used

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  • System-level packaging method and packaging structure
  • System-level packaging method and packaging structure
  • System-level packaging method and packaging structure

Examples

Experimental program
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Embodiment 1

[0030] The present invention provides a system-level packaging method, comprising the following steps:

[0031] S01. Provide a PCB board, on which a plurality of exposed first pads are formed;

[0032] S02. Provide a first device wafer, on which a first chip is formed, and the first chip has a plurality of exposed second pads;

[0033] S03, bonding the first device wafer to the PCB board, the first welding pad and the second welding pad are arranged oppositely to form a gap;

[0034] S04, using an electroplating process to form a conductive bump in the gap, and the first pad and the second pad are electrically connected through the conductive bump.

[0035] Figure 1-Figure 7 It is a structural diagram corresponding to each step of the system-in-package method in this embodiment. Please refer below Figure 1-Figure 7 The system-in-package method is described.

[0036] Please refer to figure 1 , step S01 is executed to provide a PCB board 100 on which a plurality of expose...

Embodiment 2

[0072] refer to Figure 8 This embodiment 2 provides a structural schematic diagram of another packaging method. The difference between this embodiment 2 and embodiment 1 is that after the conductive bumps 301 are formed, the PCB board 100 includes opposite front and back sides, and the first solder joint is formed. One side of the pad 101 is the front side of the PCB board 100, and the second device wafer 500 is bonded to the back side of the PCB board 100, and a second chip 501 is formed on the second device wafer 500, and the PCB board 100 and the second device wafer 500 Conductive bumps 301 or solder balls are electrically connected to each other by an electroplating process.

[0073]In this embodiment, the second device wafer 500 or other chips are bonded on the back of the PCB board 100 , and the second device wafer 500 is taken as an example for description in this embodiment. Form the exposed third welding pad 103 on the back side of the PCB board 100, form the second...

Embodiment 3

[0080] refer to Figure 9 , Embodiment 3 provides a schematic structural diagram of another packaging method. The difference between Embodiment 3 and Embodiment 1 and Embodiment 2 is that after the conductive bumps 301 are formed, the first device wafer 200 includes an opposite front and the back side, the side where the second bonding pad 202 is formed is the front side of the first device wafer 200, and the third device wafer 600 is bonded to the back side of the first device wafer 200, the third device wafer is formed with a third chip, Conductive bumps 301 or solder balls are electrically connected between the first device wafer 200 and the third chip 601 on the third device wafer 600 through an electroplating process.

[0081] In this embodiment, the third device wafer 600 or other chips are bonded on the backside of the first device wafer 200 , and the third device wafer 600 is taken as an example for description in this embodiment. On the back side of the first device ...

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Abstract

The invention provides a system-level packaging method and packaging structure. The method comprises the steps that: a PCB is provided, and a plurality of exposed first welding pads are formed on the PCB; a first device wafer is provided, wherein a first chip is formed on the first device wafer, and the first chip is provided with a plurality of exposed second welding pads; the first device wafer is bonded on the PCB, wherein the first welding pads and the second welding pads are oppositely arranged to define a gap; and conductive bumps are formed in the gap by adopting an electroplating process, wherein the first welding pads and the second welding pads are electrically connected through the conductive bumps. According to the invention, the first device wafer is bonded on the PCB, so that the connection between the PCB and the first device wafer is realized, the integration height of the device is reduced, and the utilization rate and the integration level are improved. Besides, the conductive bumps are formed between the PCB and the first device wafer through an electroplating process for electrical connection, so that the packaging process is simplified, the electrical connection efficiency is enhanced, and the conductivity is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a system-in-package method and a package structure. Background technique [0002] In different component manufacturing fields, the limited space and increasing circuit integration have put forward requirements on the manufacture of electronic products from many aspects. The size of surface mount components has been decreasing, thereby facilitating the integration of a large number of components onto printed wiring boards. Advances in design have led to very high levels of integration and eventually to stacked structures, while requirements for installation space have increased even faster than component sizes have decreased. [0003] The system-in-package module wraps a large number of electronic components, such as chips, resistors, etc., and circuits in a very small package. The biggest advantage is that it can save space and low power consumption. Wireless communicati...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L23/488H01L25/16
CPCH01L21/50H01L24/81H01L23/488H01L25/16H01L2224/818
Inventor 蔺光磊
Owner 芯知微(上海)电子科技有限公司
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