Semiconductor structure and forming method thereof

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a first substrate provided with a first surface and a second surface which are opposite to each other; forming a first dielectric layer on the first surface, wherein a first opening is formed in the first dielectric layer; sequentially forming a first conducting layer and a second conducting layer in the first opening, wherein the crystal phase proportion of the surface (1, 1, 1) of the second conducting layer is larger than that of the surface (1, 1, 1) of the first conducting layer; providing a second substrate provided with a third face and a fourth face which are opposite to each other, forming a second dielectric layer on the third face, enabling a conductive structure to be arranged in the second dielectric layer, and enabling the conductive structure to be exposed out of the surface of the second dielectric layer; and bonding the first surface of the first substrate towards the third surface of the second substrate, so as to fix the first dielectric layer and the second dielectric layer, wherein the surface of the second conductive layer and the surface of the conductive structure are fixed. The formed semiconductor structure is good in electrical stability and long in service life.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof in three-dimensional packaging technology. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the industry's requirements for device packaging density and circuit performance continue to increase. In recent years, three-dimensional packaging technology has been widely used in the manufacture of various integrated circuits because it can meet the technical requirements of high performance, low power consumption, and high integration density. [0003] In three-dimensional packaging technology, bonding is a key technology for multi-layer chip interconnection to achieve vertical stacking. Among them, the hybrid bonding technology combines metal-metal bonding and dielectric-dielectric bonding, which can effectively realize chip interconnection and stacking, whil...

AI Technical Summary

Problems solved by technology

[0006] The technical problem solved by the present invention is that for the through-hole structure with a large aspect ratio, there are problems of insufficient bonding and high process temperature required for bonding, resulting in shortened service life of the device and unstable electrical performance

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