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FinFET integrated circuit basic unit

A basic unit and integrated circuit technology, which is applied in the field of microelectronics technology and integrated circuits, can solve the problems of Lch being unable to reduce the leakage-induced potential barrier, MOSFET channel length reduction, etc., to adjust the threshold voltage and reduce the conduction Resistance, the effect of boosting the accumulation effect

Active Publication Date: 2021-12-24
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006]2. Another reason why Lch cannot be reduced is the leakage-induced barrier lowering (DIBL) effect
As a result, the reduction of their MOSFET channel length is limited
[0007]3. One of the important reasons why Lch cannot be reduced is the high field effect
In terms of the withstand voltage area of ​​the device, FinFET and GAAFET are no different from traditional MOSFETs

Method used

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Examples

Experimental program
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Effect test

Embodiment 1

[0055] Embodiment 1: Simulation and results of a highly doped nano-channel FinFET device.

[0056] This embodiment emulates a kind of highly doped nano-channel FinFET device described in claim 1, and its output characteristic curve is as follows Figure 17 , the transfer characteristic curve as Figure 18 In this embodiment, the gate electrode (101) and the gate dielectric layer (102) only wrap the channel semiconductor region (105).

[0057] Taking the width in the horizontal direction and the thickness in the vertical direction, taking the NMOS with a thickness of 14nm in the 105 region as an example, the specific parameters of its structure are introduced. The thickness of the 103 region is 20nm, the width is 6nm, the material is silicon, and the doping concentration is 1x10 20 cm -3 , the impurity is phosphorus; the thickness of the 104 region is 3nm, the width is 6nm, the material is silicon, and the doping concentration is 5x10 15 cm -3 , the impurity is phosphorus;...

Embodiment 2

[0058] Embodiment 2: Simulation and results of a highly doped nano-channel FinFET device.

[0059] This embodiment emulates a highly doped nano-channel FinFET device described in claim 2, and its output characteristic curve is as follows Figure 23 , the transfer characteristic curve as Figure 24 , the difference of this embodiment lies in the way of wrapping the gate electrode and the gate dielectric layer. The gate electrode (101) and the gate dielectric layer (102) wrap the lightly doped drain region (106), the channel semiconductor region (105) and the lightly doped source region (104).

[0060] Taking the width in the horizontal direction and the thickness in the vertical direction, taking the NMOS with a thickness of 14nm in the 105 region as an example, the specific parameters of its structure are introduced. The thickness of the 103 region is 20nm, the width is 6nm, the material is silicon, and the doping concentration is 1x10 20 cm -3 , the impurity is phosphorus...

Embodiment 3

[0061] Embodiment 3: Simulation and results of a highly doped nano-channel FinFET device.

[0062] This embodiment emulates a highly doped nano-channel FinFET device described in claim 3, and its output characteristic curve is as follows Figure 25 , the transfer characteristic curve as Figure 26 , the maximum oscillation frequency curve is as Figure 27 , the maximum oscillation frequency is 1427GHz, the fixed voltage of lightly doped source region gate electrode (108) and lightly doped drain region gate electrode (110) is 0V; the difference of this embodiment is the material of gate electrode and gate dielectric layer with the wrapping method. The gate electrode (101) and the gate dielectric layer (102) wrap the channel semiconductor region (105), the lightly doped source region gate electrode (108) and the lightly doped source region gate dielectric layer (109) wrap the lightly doped source region region (104), the lightly doped drain region gate electrode (110) and the...

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Abstract

The invention discloses a FinFET integrated circuit basic unit, which relates to the field of microelectronic technology and integrated circuits. The basic unit is of a multi-layer structure, the lowermost layer is a low-doped well region, and the low-doped well region comprises a bottom layer and ridge-shaped protrusions on the bottom layer; isolation layers are arranged on the two sides of the ridge-shaped protrusions, and the upper surfaces of the isolation layers are flush with the upper surfaces of the ridge-shaped protrusions of the low-doped well region; a drain semiconductor region, a lightly-doped drain region, a channel semiconductor region, a lightly-doped source region and a source semiconductor region are sequentially arranged along the upper surface of the ridge-shaped bulge of the lightly-doped well region, and the two side surfaces and the upper surface of the drain semiconductor region are flush with each other; gate electrodes are arranged on the two side faces and the upper surface of the channel semiconductor region, and a gate dielectric layer is arranged between the gate electrodes and the channel semiconductor region for isolation. The dielectric constants of the gate oxide layers wrapping the channel region and the N-doped region are different, and a material with a relatively large dielectric constant can be adopted in the N-region, so that the accumulation effect of multiple carriers on the surface of the N-region can be improved, the on-resistance of the N-region can be reduced, and the on-current can be increased.

Description

technical field [0001] The invention relates to microelectronic technology and integrated circuit technology, in particular to a fin field effect transistor. Background technique [0002] According to the opinion of authoritative international organizations, Moore's Law has obviously slowed down and will stop in the near future. Therefore, people have been talking about "Beyond Moore", and it seems that the era of a new generation of semiconductors will come soon. [0003] Since the birth of IC, the development of IC has been following Moore's Law for decades. However, the progress of IC chips has encountered a bottleneck in recent years. In the future, the speed of Moore's Law will be slower and slower, and the channel length Lch of the transistor will shrink slowly until it reaches 9.6nm, and the shrinking will stop. [0004] As the channel length Lch of the transistor shrinks, there are some problems to be solved: [0005] 1. The most important parameter of Moore's La...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/08H01L29/10H01L29/423H01L29/78
CPCH01L29/785H01L29/0684H01L29/0847H01L29/1033H01L29/42368
Inventor 廖永波聂瑞宏李平冯柯彭辰曦刘玉婷李垚森杨智尧刘金铭刘仰猛
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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