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LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for improving single particle burning resistance effect

An anti-single-event and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the single-event burnout effect, increase the drain buffer current of the device, etc., to prevent the single-event burnout effect and reduce the single-event burnout. Probability, electron-hole pair reduction effect

Pending Publication Date: 2021-12-31
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, when the LDMOS device is in an irradiated environment, the electron-hole pairs generated in the substrate will be collected by the drain and source, increasing the drain buffer current of the device, making the device more prone to single event burnout, so improving the traditional The single event burnout effect of LDMOS devices has become a hot issue in this research field

Method used

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  • LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for improving single particle burning resistance effect
  • LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for improving single particle burning resistance effect
  • LDMOS (Laterally Diffused Metal Oxide Semiconductor) device for improving single particle burning resistance effect

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Embodiment 1

[0067] Embodiment 1: as figure 1 As shown, the LDMOS device for effectively improving the anti-single event burnout effect of the present invention includes: a substrate 1, an N-type silicon carbide layer 2, a P1 buried silicon carbide layer 3, a P2 buried silicon carbide layer 4, a P3 buried silicon carbide layer 5, P+ source region 6, N+ source region 7, P-well region 8, P+ well region 9, N-type drift region 10, N-drain buffer region 11, N+ drain region 12, source 13, gate 14, gate oxide Layer 15, field plate 16, field oxide layer 17, drain 18. The P-type silicon carbide buried layer is located in the middle of the N-type silicon carbide buried layer 2 .

[0068] Such as figure 2 As shown, the traditional LDMOS device includes: substrate 1, P+ source region 2, N+ source region 3, P-well region 4, P+ well region 5, N-type drift region 6, N-drain buffer region 7, N+ drain region 8. Source electrode 9 , gate electrode 10 , gate oxide layer 11 , field plate 12 , field oxide ...

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Abstract

The invention discloses an LDMOS device for improving the single particle burning resistance effect, which belongs to the field of power semiconductor devices and comprises a substrate, a first silicon carbide buried layer formed on the substrate, wherein the first silicon carbide buried layer is an N-type silicon carbide buried layer; an active top layer formed on the first silicon carbide buried layer, wherein the active top layer comprises a source region, a well region, a drain buffer region, a drain region and a drift region; a device top layer formed on the surface of the active top layer, wherein the device top layer comprises a source electrode, a drain electrode, a gate oxide layer, a gate electrode, a field oxide layer and a field plate. Collection of drain electrode electrons is effectively reduced, the drain electrode buffer current is reduced, and the single-particle burning effect of the device is prevented; meanwhile, the P-type silicon carbide buried layer is added to adjust the surface electric field of the top layer silicon and reduce the electric field peak value of the drift region, so that electron hole pairs generated in the drift region are relatively reduced, the collection amount of the drain electrode and the source electrode is reduced, and the probability of single particle burning of the device is reduced.

Description

technical field [0001] The present application relates to the field of power semiconductor devices, in particular, to an LDMOS device for improving resistance to single event burnout. Background technique [0002] The LDMOS device is a power device with a double diffusion structure. This technology is implanted twice in the same source / drain region, once with a higher implant concentration (typical implant dose 1015cm -2 ) of arsenic (As), another implantation concentration is smaller (typical dose 1013cm -2 ) of boron (B). After implantation, a high-temperature push process is performed. Since boron diffuses faster than arsenic, it will diffuse farther along the lateral direction under the gate boundary to form a channel with a concentration gradient. Its channel length is determined by the two lateral diffusions. determined by the difference in distance. To increase the breakdown voltage, there is a drift region between the active and drain regions. The drift region i...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/7823H01L29/0623H01L29/0684
Inventor 王颖杨洋李兴冀杨剑群曹菲包梦恬
Owner HANGZHOU DIANZI UNIV
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