Phase-locked loop circuit of self-bias structure

Abstract

The invention discloses a phase-locked loop circuit of a self-bias structure. The phase-locked loop circuit comprises a phase frequency detector module, an integral path module, a proportional path module, an oscillator module, a frequency divider module, a starting circuit module and a self-bias module. According to the structure, the bias voltage directly provided for the oscillator module is output by an integral path, so that any external reference voltage or current is not needed, and a starting circuit is added, so that self-locking is avoided, and the reliability is improved; integral path current and oscillator module current change proportionally, so that bandwidth can be almost constant, and noise performance can be optimized; according to the proportion path, capacitance voltage division replaces a resistor in a traditional structure, and robustness is improved; either single-ended or differential voltage-controlled oscillator can be used, the self-biased oscillator is simple in structure, does not need an additional operational amplifier, and is easy for low-noise design. A power supply scheme and a frequency planning scheme of a complex SOC system clock can be effectively simplified, the freedom degree of a phase-locked loop circuit is improved, and the area is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a phase-locked loop circuit with a self-bias structure. Background technique [0002] Phase-locked loop circuits are widely used in various chips, and are indispensable core parts in the field of radio frequency microwave, digital-analog hybrid field and pure digital field. The function and performance of the phase-locked loop play a decisive role in the success or failure of the entire chip. System-on-chip (SOC) clock schemes are generally divided into two categories: one type provides various required frequencies through a single phase-locked loop through a complex post-divider; the other type consists of multiple distributed phase-locked loop circuits for each digital The IP provides the required clock locally. The former type of solution greatly increases the complexity and power consumption of the phase-locked loop design in the scenario where multiple crys...

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Problems solved by technology

In addition, when providing clocks for digital IP (such as audio, video), digital IP power supply voltages are often low (such as sub-1V), although PLLs can be implemented at sub-1V, traditional bandgap references often require high voltage 1.8 V or 3.3V to work

On the one hand, this leads to complex power supply topology when pure digital IP integrates phase-locked loops, and additional high-voltage power supplies are required. Difficulty in isolation

Finally, when the SOC system clock uses a distributed phase-locked loop, it is often desirable to multiplex the phase-locked loop circuit to improve development efficiency, but the change in the output frequency of the phase-locked loop will lead to changes in the overall noise performance, which leads to the Each phase-locked loop needs to adjust the parameters separately, which reduces the efficiency

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