High-voltage MOS tube and manufacturing method thereof

Abstract

The invention provides a manufacturing method of a high-voltage metal oxide semiconductor tube. The manufacturing method comprises the following steps: providing a substrate, forming a shallow trench isolation structure on the substrate, and forming a liner oxide layer on the surface of the substrate; forming a mask layer; and etching the mask layer, the liner oxide layer, the shallow trench isolation structure and the substrate so as to obtain a stepped trench in the shallow trench isolation structure and the substrate and form a gate oxide layer in the stepped trench. According to the invention, the substrate in a high-voltage device region and the shallow trench isolation structure are etched at the same time to form the stepped trench, so that the top surface of the gate oxide layer deposited in the stepped trench tends to be flush with the top surfaces of the gate oxide layers in the regions of other devices (medium-voltage and low-voltage devices) around the stepped trench, therefore, the height uniformity of the pseudo polysilicon gate formed above the subsequent gate oxide layer is improved, the condition that the pseudo polysilicon gate in a high-voltage device region is excessively and mistakenly ground in the subsequent ILD0CMP process is avoided, and the completeness of the metal gate is ensured.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices, in particular to a high-voltage MOS transistor and a manufacturing method thereof. Background technique [0002] As the size of transistors continues to shrink, HKMG (high-K insulating layer + metal gate) gradually replaces the original configuration of silicon dioxide insulating layer + polysilicon gate, and becomes an indispensable part of the process below 28nm. [0003] The gate oxide process in the existing high-voltage MOS transistor is to directly grow the gate oxide layer on the surface of the silicon substrate, but because the thickness of the gate oxide layer of the high-voltage MOS transistor is smaller than that of other devices on the same wafer (such as medium-voltage and low-voltage MOS transistors) The thickness of the gate oxide layer of the high-voltage MOS tube is much thicker, so in the high-voltage MOS tube, the high-voltage gate oxide layer grown acco...

AI Technical Summary

Problems solved by technology

Among them, when performing the ILD0CMP (Interlayer Insulation Chemical Mechanical Polishing) process, because all devices on the same wafer are polished at the same time, the pseudo polysilicon gate above the gate oxide layer of the high-voltage MOS transistor area is higher than that of the medium-voltage and low-voltage MOS. The dummy polysilicon gate in the tube region is excessively mispolished, which affects the formation of the metal gate in the high-voltage MOS tube

Even in extreme cases, after the ILD0 CMP process, the pseudo-polysilicon gate in the high-voltage device region will be completely ground off, thereby affecting the filling of metal materials, that is, affecting the formation of the metal gate in the high-voltage MOS tube, which will easily lead to a decrease in the performance of the device. fail

Images