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TSV back exposed hole structure and preparation method thereof

A hole structure and backside technology, applied in the field of microelectronics, can solve the problems of high cost and poor uniformity of exposed holes in the wafer, and achieve the effects of high cost, lower technical threshold and high mechanical strength.

Pending Publication Date: 2022-01-28
珠海天成先进半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to overcome the shortcomings of high cost and poor uniformity of exposed holes in the wafer in the integrated circuit manufacturing process in the above-mentioned prior art, and provide a TSV back exposed hole structure and preparation method

Method used

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  • TSV back exposed hole structure and preparation method thereof
  • TSV back exposed hole structure and preparation method thereof
  • TSV back exposed hole structure and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] A TSV rear exposed hole structure, comprising a substrate 100, the upper surface of the substrate 100 is provided with a front insulating layer 1, and the upper surface of the substrate 100 is provided with a TSV blind hole; the front insulating layer 1 is laid with a front metal wiring layer 5 The TSV blind hole is filled with conductive filler 4, and the front metal wiring layer 5 is connected to the conductive filler 4; the lower surface of the substrate 100 is provided with a second through hole, and the second through hole is located directly below the TSV blind hole, and It is coaxial with the TSV blind hole, and the bottom of the TSV blind hole communicates with the second through hole. The lower surface of the substrate 100 is provided with a back insulating layer 6 , and a back metal wiring layer 7 is laid on the back insulating layer 6 . The back metal wiring layer 7 is located at one end of the second through hole and communicates with the second through hole....

Embodiment 2

[0039] Except for the following content, all the other contents are the same as in Example 1.

[0040] The inner wall of the TSV blind hole is provided with an insulating layer 2 in the blind hole, and an adhesive layer 3 in the blind hole is arranged between the insulating layer 2 in the blind hole and the conductive filler 4 . There are three TSV blind holes; the front metal wiring layer 5 has multiple layers, and the back metal wiring layer 7 has multiple layers. The height of the second through hole in the vertical direction is 3 μm. The diameter of the second through hole is equal to the diameter of the TSV blind hole.

Embodiment 3

[0042] Except for the following content, all the other contents are the same as in Example 1.

[0043] The height of the second through hole along the vertical direction is 6 μm; the diameter of the second through hole is larger than the diameter of the TSV blind hole.

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Abstract

The invention discloses a TSV back exposed hole structure and a preparation method thereof, and belongs to the technical field of microelectronics. A TSV blind hole is formed in the upper surface of the substrate, a second through hole is formed in the lower surface of the substrate, the second through hole is located under the TSV blind hole and is coaxial with the TSV blind hole, and the bottom of the TSV blind hole is communicated with the top of the second through hole. According to the structure, front and back conduction of the TSVs is realized through interconnection of the front and back TSV holes, so that the substrate is provided with front and back electrical interconnection channels, and the technical requirements of 2.5 D or 3D integration are met. Meanwhile, the length of the TSV in the substrate is increased, and more substrates of the substrate can be reserved, so the substrate has higher mechanical strength. According to the preparation method of the TSV back exposed hole, a common CMP process in the industry is omitted, the process cost is remarkably reduced, the technical threshold is reduced, and the problems that the TSV back exposed hole is high in cost, the process is complex, and the uniformity in a wafer is poor are solved.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to a TSV rear exposed hole structure and a preparation method. Background technique [0002] With the continuous increase in the process difficulty and investment amount of integrated circuit manufacturing, and the approach of the development limit determined by physical laws such as power consumption and quantum effects, the development of "Moore's Law" has encountered major challenges, and more than Moore's Law (More than Moore's Law) has gradually emerged. Moore) development direction. Unlike the quantity and integration that continue Moore's Law (More Moore), it mainly focuses on "diversity of functions". Using TSV-based three-dimensional integration process technology to integrate chips of different materials or functions in 2.5D / 3D to realize a complete functional module. The TSV three-dimensional integration technology based on vertical TSV through-hole interconnecti...

Claims

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Application Information

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IPC IPC(8): H01L23/48H01L21/768
CPCH01L23/481H01L21/76898
Inventor 何亨洋李宝霞吴玮
Owner 珠海天成先进半导体科技有限公司
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