Packaging method of fan-out wafer level packaging structure

Abstract

The invention provides a packaging method of a fan-out type wafer level packaging structure, which comprises the following steps of: providing more than two semiconductor chips and bonding the semiconductor chips on a bonding layer; packaging the semiconductor chip by using a plastic packaging layer; removing the bonding layer, and forming a rewiring layer on the semiconductor chips to realize interconnection of the semiconductor chips; the rewiring layer comprises at least one sub-rewiring layer which is stacked in sequence. The method for forming the sub-rewiring layer comprises the following steps: forming a dielectric layer on a semiconductor chip; forming a through hole in the dielectric layer by adopting a photoetching process; baking the dielectric layer with the through hole to eliminate warping of the dielectric layer around the through hole; curing the dielectric layer; and forming a patterned metal wiring layer corresponding to the through hole in the through hole and on the dielectric layer, and forming a metal bump on the patterned metal wiring layer. According to the method, the morphology of the dielectric layer around the through hole can be effectively improved, the upwarp of the dielectric layer around the through hole is eliminated, and the electrical connection performance of the rewiring layer formed subsequently and the semiconductor chip is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular to a packaging method of a fan-out wafer level packaging structure. Background technique [0002] With the rapid development of the integrated circuit manufacturing industry, people's requirements for the packaging technology of integrated circuits are also increasing. The existing packaging technologies include ball grid array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP) ), three-dimensional packaging (3D) and system in package (SiP), etc. Among them, wafer-level packaging (WLP) is gradually adopted by most semiconductor manufacturers due to its outstanding advantages. All or most of its process steps are completed on silicon wafers that have completed the previous process, and finally the wafer Direct dicing into separate individual devices. Wafer-level packaging (WLP) has its unique advantages: ① high packaging processing efficiency, m...

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a packaging method of fan-out wafer level packaging structure, which is used to solve the problem of the fan-out wafer level packaging in the prior art after the semiconductor chip is plastic-encapsulated. Warping of the wafer will cause the risk of poor contact between the subsequent rewiring layer and the semiconductor chip, which will affect the yield of the wafer package, etc.

Images