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3D NAND memory based on two-dimensional material and preparation method thereof

A 3DNAND, two-dimensional material technology, applied in the semiconductor field, can solve the problems of different memory cell threshold voltage fluctuations, memory cell on-state current reduction, easy to cause reliability problems, etc., to achieve improved storage density, high on-state current, high The effect of integration

Pending Publication Date: 2022-03-18
SHANXI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, polysilicon material is used as the channel layer because there are crystal boundaries in polysilicon, which will generate charge traps in the channel layer, so that as the number of stacked layers of word lines increases, the on-state current of the memory cell will increase with the number of stacked layers. increase and decrease rapidly, which can lead to dyslexia
[0005] When polysilicon material is used as the channel layer material, a larger on-state current can be achieved by increasing the grain size of polysilicon, however, due to the random distribution of charge traps in polysilicon, the increase in grain size will lead to different memory cells. The fluctuation of the threshold voltage, and the distribution becomes wider, which is easy to cause reliability problems

Method used

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  • 3D NAND memory based on two-dimensional material and preparation method thereof
  • 3D NAND memory based on two-dimensional material and preparation method thereof
  • 3D NAND memory based on two-dimensional material and preparation method thereof

Examples

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Embodiment 1

[0036] Such as figure 1 , figure 2 As shown, a 3D NAND memory based on two-dimensional materials of the present invention includes a substrate 101, a stacked structure 102, a first annular channel 105, a second annular channel 106, a channel hole 107, and a circular hole 108 ;

[0037] The stacked structure 102 is located on the upper surface of the substrate, and the stacked structure 102 is composed of a plurality of insulating layers 104 and conductive layers 103 stacked alternately, such as 32 layers, 64 layers, 256 layers and so on.

[0038] The conductive layer 103 is located on the upper surface of the substrate 101, and a first annular channel 105, a second annular channel 106, and a channel hole 107 are concentrically etched from the outside to the outside of the stacked structure 102, and The second annular channel 106 communicates with the channel hole 107, the first annular channel 105 and the second annular channel 106 are filled with an insulating medium, and ...

Embodiment 2

[0044] Such as image 3 Shown, a kind of preparation method of the 3D NAND memory based on two-dimensional material comprises the following steps:

[0045] Step 1, prepare the substrate 101, use the upper surface of the substrate 101 as the basal plane, grow metal Mo, and generate 1T metal phase MoTe by tellurization 2 , constitute the conductive layer 103, and then adopt a thin film deposition process to deposit and prepare a layer of silicon oxide layer on the conductive layer 103, as the insulating layer 104, and then grow repeatedly in sequence to obtain the laminated structure 102 of the conductive layer 103 and the insulating layer 104, and obtain Such as Figure 4 the structure shown;

[0046] Step 2, perform the first annular etching on the obtained laminated structure 102, and fill the insulating medium in the etched trench to obtain 1T MoTe in the horizontal direction 2 Metallic gate layer and barrier layer;

[0047] This step is to etch the laminated structure a...

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Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a 3D NAND memory based on a two-dimensional material and a preparation method thereof. In order to solve the problem that an existing 3D NAND memory is poor in electrical performance, a stacked structure of the memory is located on the upper surface of a substrate and is composed of a plurality of insulating layers and conductive layers which are alternately stacked, the conductive layers are located on the upper surface of the substrate, and the conductive layers are located on the upper surface of the substrate. A first annular channel, a second annular channel and a channel hole are concentrically etched on the laminated structure from outside to outside, the second annular channel is communicated with the channel hole, the first annular channel and the second annular channel are filled with insulating media, the channel hole is filled with a semiconductor two-dimensional material, a round hole is etched on the semiconductor two-dimensional material, and the round hole is filled with insulating media. The preparation method comprises the following steps: taking a substrate as a base to obtain a laminated structure with alternate conducting layers and insulating layers, then carrying out two times of annular etching and circular hole etching, and filling corresponding materials in corresponding channels.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a 3D NAND memory based on two-dimensional materials and a preparation method thereof. Background technique [0002] 3D NAND memory is a flash memory device with a three-bit stacked structure. Multi-layer data storage units are stacked vertically, and its storage core area is composed of vertical channel tubes with alternately stacked metal gate layers and insulating layers. This technology can construct a storage device with a higher storage capacity, which can accommodate a higher storage capacity in a smaller space. Under the same area condition, the more vertically stacked metal gates, the higher the storage density and capacity of the device. bigger. [0003] Existing 3D NAND memory has problems of poor electrical performance, for example, the on-state current is small and unstable, and the threshold voltage fluctuates greatly. The reason why the 3D NAND ...

Claims

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Application Information

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IPC IPC(8): H01L27/1157H01L27/11575H01L27/11582
CPCH10B43/50H10B43/35H10B43/27
Inventor 韩拯陈茂林任乃杰
Owner SHANXI UNIV
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