ATE test equipment-oriented novel integrated circuit test excitation generation method

Abstract

The invention discloses a novel integrated circuit test excitation generation method for ATE test equipment, and the method comprises the following steps: step 1, constructing a full-piece design model, step 2, constructing a simulation verification environment, step 3, writing a test file, and step 4, carrying out simulation verification. The method comprises the following steps: step 1, carrying out simulation on different verification platforms based on behavior levels according to a four-layer structure to generate different levels of test incentives, and step 5, carrying out fusion to form a complete test incentive, and fusing the test incentives generated on the different verification platforms based on an application layer framework according to a calling and hierarchical relationship to form the complete test incentive. According to the method, the difficulty and complexity of test excitation generation environment construction can be reduced, the compatibility and adaptability of test excitation environment construction are improved, the test excitation generation time is shortened, the test excitation generation efficiency is improved, and the intuition and readability of information in a test excitation file are improved.

Description

technical field [0001] The invention relates to a novel integrated circuit test excitation generation method for ATE test equipment, and belongs to the technical field of integrated circuit test. Background technique [0002] Integrated circuit testing is an important link in the production of integrated circuits. All integrated circuits need to be tested to confirm that their functions and performance meet the requirements before they can be put on the market. ATE is the abbreviation of automatic test equipment. At present, most integrated circuit tests are completed on integrated circuit automatic test equipment (ATE). Integrated circuit ATE equipment develops along with integrated circuits. The basic principle of ATE equipment for circuit testing It is to apply the test stimulus in the waveform format to the input signal periodically, and compare the output result of the output signal with the expected result of the test stimulus. If they are consistent, the test result i...

AI Technical Summary

Problems solved by technology

[0005] (1) The problem of long test stimulus generation time: the complexity of the integrated circuit design verification platform continues to increase, and the time to generate test stimulus based on the signal layer is getting longer and longer. The generation time of a test stimulus has reached tens of hours or even Hundreds of hours, the generation efficiency is getting lower and lower, which seriously affects the efficiency of circuit testing and debugging, and further affects the time to market of the circuit;

[0006] (2) The complex issue of test stimulus generation environment construction: testing the current high-performance integrated circuit design verification platform is based on the mainstream hierarchical software and hardware collaborative verification environment. The software environment such as verification and command verification and the mixed verification environment, in this environment, it is relatively complicated and difficult to build a single test stimulus generation platform based on the signal layer, it takes a long time, and the labor cost is relatively high;

[0007] (3) The problem of unintuitive test stimulus information: The information contained in the current test stimulus files is not intuitive and opaque. For example, the test stimulus based on VCD format is a common format, an ASCII file, which contains header information, variable presets, etc. Definition and variable value information, which is a text in a signal layer descriptive language, is like a black box for test engineers, unable to understand the specific content of the test and the specific process of the test, and it is difficult to compare the test failure with the simulation link directly to the process

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