General detection device and method for high-speed digital interface of integrated circuit

Abstract

The invention discloses a general detection device and method for integrated circuit high-speed digital interface, which comprises a middle-low speed digital test channel motherboard and a high-speed digital interface test channel daughter board, and the middle-low speed digital test channel motherboard includes a test processor, a medium-low speed The test channel unit is provided with a high-speed test channel sub-board interface on the medium and low-speed test channel group; the high-speed digital interface test channel sub-board includes a test processor motherboard interface, an FPGA code configuration generator, and a high-speed test channel of a configurable interface protocol Driving FPGA, high-speed test channel unit, and reconfigurable test data processor, the motherboard interface of the test processor is connected to the high-speed test channel sub-board interface of the medium and low-speed test channel group. The invention can not only meet the low-medium speed test requirements of general IO ports, but also can meet the test of high-speed interfaces. It can not only obtain the high flexibility of the FPGA solution, but also obtain the lower cost of the middle and low-end ATE equipment.

Description

technical field [0001] The invention relates to a general detection device and method for a high-speed digital interface of an integrated circuit, and belongs to the technical field of chip detection. Background technique [0002] As modern digital integrated circuits are increasingly designed with high-speed digital interfaces, such as MIPI, HDMI, Serdes, DDR, USB, PCIe, etc. The data transmission speed of this type of digital interface varies from several hundred Mbps to several Gbps, and the physical interface type ranges from LVCMOS, LVDS, to LVPECL or CML. In ATE (Auto Test Equipment, automatic test equipment), the detection of such signals faces a relatively large challenge. One is the high test frequency. The data transmission speed of hundreds of Mbps to Gbps can cause the interface level change frequency to reach as high as hundreds of MHz to gigahertz. If the traditional ATE Timing Generator (TG) is used for testing, the equipment cost is too high (basic The hig...

AI Technical Summary

Problems solved by technology

The data transmission speed of hundreds of Mbps to upper Gbps causes the interface level change frequency to be as high as several hundred MHz to upper GHz. If the traditional ATE Timing Generator (TG for short) is used for testing, the equipment cost is too high (basic It needs the most high-end ATE, or needs to sacrifice a large number of test channels in exchange for a higher test data rate)

The second is the complex interface timing and protocol

The test pattern will be very complicated, and it also has high requirements for the tester's test program development ability

The third is a variety of interface level modes, and the general ATE digital test IO port cannot meet the requirements

In short, various traditional test solutions cannot have both low cost of testing, high flexibility of test development, low complexity of test development and high coverage of test solutions

Various problems will push up the test cost of the design company in the IC test process

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