Semiconductor structure, preparation method thereof and control system corresponding to semiconductor structure

Abstract

The embodiment of the invention relates to a semiconductor structure, a preparation method thereof and a control system corresponding to the semiconductor structure. The method comprises the steps that a substrate is provided, wherein the substrate comprises a preset structure and an etching material layer located on the preset structure; forming a photoresist pattern layer on the etching material layer, wherein the photoresist pattern layer comprises a first opening; obtaining a first deviation between the bottom of the first opening and the top of the preset structure on a first plane, wherein the first plane is parallel to the surface of the substrate; performing patterning processing on the etching material layer based on the photoresist pattern layer to obtain a second opening; acquiring a second deviation between the bottom of the second opening and the bottom of the first opening on the first plane; according to the second deviation and the first deviation, a photoetching compensation value is obtained, and the photoetching compensation value is used for correcting the first deviation so as to eliminate dislocation of the second opening and the preset structure on the first plane. By using the lithographic compensation value to correct the first deviation, the influence of the lithographic error and the etching error on the misalignment can be eliminated.

Description

technical field [0001] Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to a semiconductor structure, a method for fabricating the same, and a control system corresponding to the semiconductor structure. Background technique [0002] With the development of semiconductor technology, the requirements for high aspect ratio etching are getting higher and higher, due to the difference in incoming wafers, the difference in calibration between different lithography stations, and the uneven distribution of plasma during the etching process. , causing the dislocation between the upper structure and the lower structure of the semiconductor device formed on the process wafer, resulting in the failure of the semiconductor device, batch-to-batch feedback control after a simple etching process or a batch after simple lithography and development Feedback control cannot completely solve all the dislocations between the upper and lowe...

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Problems solved by technology

[0002] With the development of semiconductor technology, the etching requirements for high aspect ratio are getting higher and higher. Due to the difference of incoming wafers, the difference of calibration between different photolithography stations, and the uneven distribution of plasma during etching , so that there is a dislocation between the upper structure and the lower structure of the semiconductor device formed on the process wafer, which leads to the failure of the semiconductor device. The batch-to-batch feedback control after the simple etching process or the batch after the simple photolithography development Feedback control cannot completely solve all dislocations between the upper structure and the lower structure, and may even over-regulate, making the dislocation worse and affecting the yield of semiconductor devices. How to solve the problem of the upper structure and lower structure of semiconductor devices before The dislocation problem of the

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