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Method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing same structures and electric field generator/modulator

An electric field generator, semi-conductive technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve complex problems

Inactive Publication Date: 2004-10-13
THIN FILM ELECTRONICS ASA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although photolithography can provide higher resolution, it is complex and typically involves wet chemical etching steps, which is undesirable in the mass production of multilayer organic thin film structures

Method used

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  • Method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing same structures and electric field generator/modulator
  • Method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing same structures and electric field generator/modulator
  • Method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing same structures and electric field generator/modulator

Examples

Experimental program
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example 1

[0062] Figure 6 It shows that the forward-biased pn junction diode with conductive or semiconductive or conductive and semiconductive structure produced according to the method of the present invention is composed of four sublayers SS1-SS4 by thin film technology. Layers SS2 and SS3 contain active semiconducting material sandwiched between electrodes 11 in sublayers SS1 and SS4, respectively. The semiconductor material 10 in the sublayer SS2 is an n-type doped semiconductor, while the adjacent active material 10' in the sublayer SS3 is a p-type doped semiconductor. Electrodes 11 in sub-layers SS1 and SS4 are in contact with lateral conductive structures or conductive channels 9 in the same layer. Figure 6 The thickness of a single layer of the diode structure is typically 100 nm, and the thickness of the entire multilayer structure thus formed is less than 1 micron. The lateral extent of the diode structure area depends on the use with eg Figure 2a The spatial resolution ...

example 2-M

[0063] Example 2 - MOSFET

[0064] Figure 7 It schematically shows a MOSFET used in the present invention, which is made entirely of organic materials by thin film technology. The gate electrode 12 provided in the sublayer SS1 is connected to the lateral conductive structure 9 , while the sublayer SS2 constitutes the gate insulating layer 13 . Sub-layer SS3 provides semiconducting active material 10 and is aligned with gate electrode 10 . Source and drain electrodes 14 are provided by the uppermost layer SS4 and are connected to lateral conductive structures 9 in the same layer. Each sublayer consists of either a conductive structure or a semiconductive structure or a conductive structure and a semiconductive structure and a dielectric region. The thickness of this MOSFET can be 1 / 2 μm, and the range that can be realized by the current technology in the plane is from at most several microns to less than 1 μm, as described in Example 1.

example 3

[0065] Example 3 - CMOS Logic Inverter

[0066] Figure 7 The MOSFET structure can now be used in logic gate circuits such as logic inverters in CMOS technology such as Figure 8 shown. This inverter is formed by connecting the source and drain electrodes of an n-MOSFET and a p-MOSFET in parallel in a back-to-back structure with a common gate electrode. For this purpose, a longitudinal conductive structure 15 is produced, which is connected to the electrode 14' through all the individual sublayers SS1-SS7. The output signal of the inverter is sent from the conductive structure 15 to the horizontal conductive structure 9 on the left in the figure. The common gate 12 of the MOSFET receives an input signal through the lateral conductive structure 9 in the right sublayer SS4 in the figure. The thickness of all sublayers is then less than 1 micron, and the typical thickness achieved is about 0.7 µm, while the lateral extent of the inverter will have the front combined Figur...

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Abstract

In a method for generating electrical conducting or semiconducting structures in two or three dimensions in a matrix which comprises two or more materials in spatially separated material structures, an electric field is applied to the separate material structure or the field-modulated spatially according to a protocol which represents a predetermined pattern of electrical conducting or semiconducting structures which are generated in the material structure in response to the field. The matrix composed by the material structures will hence comprise structures of this kind in three dimensions. In a method for global erasing an electric field is applied to the matrix until the materials in the matrix in response to the field in their entirety arrive in a non-conducting state. In an electric field generator / modulator (EFGM) which can be used for patterning and generating electrical conducting or semiconducting structures, two electrode means (E1;E2) comprise parallel strip electrodes (21;22) provided mutually spaced apart in parallel planes such that the electrodes (21, 22) form a matrix-like arrangement. The electrode means (E1;E2) are over cross-connection devices (24, 25) connected with a power supply (23). EFGM (20) is adapted for receiving a thin-film material between the electrode devices (E1, E2) in order to generate said structures.

Description

technical field [0001] The present invention relates to a method for producing two-dimensional or three-dimensional conductive or semiconductive or conductive and semiconductive structures in a composite matrix, wherein the matrix consists of spatially separated homogeneous material structures composed of one or more materials, A material in which a specific physical or chemical state or physical and chemical change occurs in response to supplied energy, thereby causing a transition from a non-conducting state to a conducting state or a semiconducting state or a conducting state and a semiconducting state, or vice versa , or a transition in the material's conduction mode, where each material structure is made in the form of a thin layer. The invention also relates to a method for the comprehensive erasure of produced two-dimensional or three-dimensional conductive or semiconductive or conductive and semiconductive structures in a composite matrix, wherein the matrix is ​​a spa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3205H01L21/02H01L21/26H01L21/336H01L21/64H01L21/768H01L21/822H01L21/8238H01L23/52H01L27/092H01L29/06H01L29/786H01L29/861H01L51/05H01L51/40
CPCH01L21/76888H01L21/8221H01L2924/0002H01L51/0001H01L21/76894H01L21/768Y10T29/41H01L51/0024H10K71/50H01L2924/00H01L21/26H10K71/00
Inventor P·-E·诺尔达尔G·I·莱斯塔德H·G·古德森
Owner THIN FILM ELECTRONICS ASA
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