Semiconductor memory
A semiconductor and memory technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems such as difficulty in practical application, increased electrical interference of adjacent memory cells, and difficult processing and manufacturing techniques.
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Embodiment 1
[0066] figure 1 is the layout of the DRAM cell array of the embodiment of the present invention, figure 2 and image 3 respectively figure 1 A-A' and B-B' profiles. By processing the p-type silicon substrate 1, a columnar silicon layer 2 is formed at the position of each memory cell MC. The memory cell MC is composed of a vertical MOS transistor formed using the columnar silicon layer 2 .
[0067] That is, the columnar silicon layer 2 is formed around the gate electrode through the gate insulating film 3, the n+ type drain diffusion layer 5 is formed on the upper end part, and the n+ type source diffusion layer 6 is formed on the lower end part, and each memory cell MC The transistors are constructed as NMOS transistors. This transistor structure is called "SGT", and was proposed by H. TaKato et al. in the paper "Impact of Surrounding Gate Transistor (SGT) for high density LSI's" (IEEE Transactions on Electron Devices, vol.38, No.3, pp.573-577, March 1991) published.
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Embodiment 2
[0101] In the first embodiment described above, a transistor having an SGT structure in which the side peripheral surface of the columnar silicon layer is used as the channel region is used as the memory cell. On the contrary, in Embodiment 2, a transistor of the columnar silicon layer is also used as the memory cell MC, but the structure of the transistor is Figure 21 that kind of structure. That is, a convex columnar silicon layer 102 is formed on a silicon substrate 101 as an active layer, and the columnar silicon layer 102 is transversely cut, and gate electrodes 104 opposite to each other through a gate insulating film 103 are arranged on the upper surface and both sides. Drain and source diffusion layers are formed on both sides of the gate electrode 104 . However, an insulating film is buried on the bottom of the columnar silicon layer 102 to maintain a floating state.
[0102] Figure 22 Represent the layout of the DRQM cell array of this embodiment, Figure 23 an...
Embodiment 3
[0111] Figure 31 It is an embodiment in which the memory cell MC is further formed with a different transistor structure. With respect to the active layer 202 formed on the silicon substrate 201, a gate insulating film 203 is formed on the upper, lower, and side surfaces thereof, and the gate electrode 204 traverses the active layer 202, and is connected to the upper, lower, and side surfaces of the active layer 202. Relatively equipped. Then, source and drain diffusion layers are formed on both sides of the gate electrode 204 . In the figure, the state where the active layer 202 is floating from the substrate 201 is shown, but actually, as described later, since the structure is produced by using a technique of forming holes inside the silicon substrate, the active layer 202 is not floating. out.
[0112] In the case of this embodiment, one NMOS transistor is used as a memory cell MC to constitute a DRAM cell array, and data writing and reading are the same as in the firs...
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