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Structure of flash memory element and making method thereof

A manufacturing method and component technology, which are applied to the structure of memory components and the manufacturing field thereof, can solve the problem of insurmountable bit line load being too high, and achieve the effects of avoiding short channel effect, avoiding bit line load, and avoiding breakdown leakage

Inactive Publication Date: 2006-07-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If high-concentration doping is used to make shallow junction bit lines to avoid problems such as short channel effects and breakdown leakage caused by too deep junctions, it cannot be overcome due to the limitation of solid solubility. Too high bit line loading problem

Method used

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  • Structure of flash memory element and making method thereof
  • Structure of flash memory element and making method thereof
  • Structure of flash memory element and making method thereof

Examples

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Effect test

no. 1 example

[0030] Figure 2A to Figure 2H , is a schematic cross-sectional view of a manufacturing process of a memory device according to an embodiment of the present invention.

[0031] Please refer to Figure 2A Firstly, a gate oxide layer 202 , a gate conductive layer 204 and a top cap layer 206 are sequentially formed on a provided substrate 200 . Wherein, the material of the gate conductive layer 204 is, for example, polysilicon. The material of the cap layer 206 is, for example, silicon nitride.

[0032] Then, please refer to Figure 2B , pattern the top cap layer 206 , the gate conductive layer 204 and the gate oxide layer 202 to form a plurality of gate structures 208 . Then, an isolation spacer 210 is formed on the sidewall of the gate structure 208 . Wherein, the method of forming the isolation spacer 210 is, for example, depositing a conformal isolation layer first, and then etching back the isolation layer by dry etching.

[0033] Then, please refer to Figure 2C A bu...

no. 2 example

[0042] Figure 3A to Figure 3H , is a schematic cross-sectional view of a manufacturing process of a memory element according to another embodiment of the present invention.

[0043] Please refer to Figure 3A Firstly, a gate oxide layer 302 , a gate conductive layer 304 and a top cap layer 306 are sequentially formed on the provided substrate 300 . Wherein, the material of the gate conductive layer 304 is, for example, polysilicon. The material of the cap layer 306 is, for example, silicon nitride.

[0044] Then, please refer to Figure 3B , pattern the top cap layer 306 , the gate conductive layer 304 and the gate oxide layer 302 to form several gate structures 308 . Then, a buried bit line 312 is formed in the substrate 300 on both sides of the gate structure 308 . A method for forming the buried bit line 312 is, for example, to use the gate structure 308 as a mask to perform an ion implantation step.

[0045] Wherein, when the line width of the gate structure 308 is 0....

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Abstract

A flash memory element structure is composed of a grid, a built-in position line, a rising position line, a separated clearance wall a character line, in which the grid is arranged on a ground. The built-in position line is set on the ground at both sides of the grid structure, the rising position line is at the built-in position line, the separation clearance wall is designed at the sidewall of the grid for separating the grid and the rising position line and the character line on the ground electrically connected with the grid and isolated with the rising position line by an insulation layer.

Description

technical field [0001] The present invention relates to a structure of a memory element and a manufacturing method thereof, and in particular to a structure of a memory element capable of reducing the resistance of buried bit lines and a manufacturing method thereof. Background technique [0002] Memory, as the name suggests, is a semiconductor device used to store data or data. In the storage of digital data, we usually use bits to form the capacity of memory. Each unit used to store data in the memory is called a storage unit (Cell). The specific location of the storage unit among the tens of thousands of storage bits is called an address. In other words, the storage units are arranged in an array in the memory, and each combination of row and column represents a specific storage unit address. Wherein, several memory cells in the same line or in the same column are connected in series with a common wire. The wire connecting the memory cells is called a word line, and a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/105H01L21/8239H01L27/10H10B99/00
Inventor 林宏穗赖汉昭卢道政
Owner MACRONIX INT CO LTD