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Method for forming multiple wire connection by using photoresist layer

A photoresist layer and wire connection technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of organic dielectric layer damage, copper ion diffusion and entry, and reduce reliability, so as to reduce damage Probability, omitting the etching process, and avoiding the effects of RC hysteresis

Inactive Publication Date: 2006-12-13
GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the dielectric constant value of organic polymer materials is lower than that of inorganic polymer materials, it has great potential for development, but organic polymers encounter some problems in semiconductor processes, such as copper damascene process in removing photoresist and residues, However, it will cause damage to the organic dielectric layer, or copper ions may diffuse into the dielectric layer, causing leakage and reducing reliability.

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  • Method for forming multiple wire connection by using photoresist layer
  • Method for forming multiple wire connection by using photoresist layer
  • Method for forming multiple wire connection by using photoresist layer

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Embodiment Construction

[0023] The structural features and beneficial effects achieved by the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] The invention provides a method for forming multiple wire connections by using a photoresist layer, which does not require multiple plasma etching processes for forming multiple wire connections in common processes, which causes etching damage to the inner metal dielectric layer , and the present invention uses an air bridge with a dielectric constant value of 1 as the inner metal dielectric layer to effectively reduce the resistance and capacitance.

[0025] Figure 1 to Figure 6 It is a schematic diagram of each step of the embodiment of the present invention. Here, the key point of the present invention is to use a photoresist layer to form a method for multiple wire connections, and to form a three-layer wire connection for a detailed description of the process. The type of MOS device...

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Abstract

This invention provides one multiple layer wire connection method by etching layer, which comprises the following steps: forming one etching terminal layer and the first light etching layer on the semi-conductor base with MOS elements; processing the etching step on the first light etching layer to form one first groove; depositing one first conductor layer on the first groove and processing first flattening; forming first bottom reflection layer and one second light etching layer on the conductor base; forming one second groove with the pattern process on the second light etching layer; depositing one second conductor layer on the second groove and processing one flattering process; final removing the first and second light etching layer to get one multiple-wire connection.

Description

technical field [0001] The invention relates to a method for forming multiple wire connections, in particular to a method for forming multiple wire connections by using a photoresist layer. Background technique [0002] With the rapid increase in the integration of semiconductor components, the surface of a chip with a size of only 2 square centimeters cannot provide enough area to make the required metal interconnection layer (interconnect). Therefore, the process design must develop the interconnection structure vertically upwards. Thus, a multi-level metallization interconnection structure is formed. An integrated circuit requires five layers of metal when the component size is 0.25 microns. Therefore, when the line width (linewidth) and pitch (pitch) shrink, the interconnection resistance and inter-line capacitance will also increase, resulting in the RC delay effect, resulting in a decrease in signal transmission speed and an increase in crosstalk noise. Large, increa...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/027
Inventor 李嘉秩叶双凤杨织森廖传钦
Owner GRACE SEMICON MFG CORP