Semiconductor device containing liner structure

Abstract

A semiconductor device which includes an improved liner structure formed in a via having extended sidewall portions and a bottom penetrating a metal line. The liner structure includes two liner layers, the first being on the via sidewalls, but not the bottom, and the second being on the first layer and the extended sidewall portions and bottom of the via. A method of making the liner structure, in which the first layer is deposited prior to an etching or cleaning step, which extends the via into the metal line, is also disclosed.

Description

technical field [0001] The present invention generally relates to semiconductor devices and methods of manufacturing the same. In particular, the present invention relates to improved liner structures featuring sacrificial elements particularly suited for copper metallurgy. Background technique [0002] The interconnect structure of a semiconductor device consists of layers (wiring layers) containing conductive lines separated by interlayer dielectric layers. The wires are electrically separated from each other by a dielectric layer. The wires in the wiring layers are interconnected by conductive vias extending from the wires in one wiring layer, through the interlayer dielectric layer, to the wires in the second wiring layer. In modern semiconductor devices, wires are partially embedded or embedded in dielectric layers. [0003] As the speed of modern semiconductor devices increases, interlayer wiring capacitance has become a problem that has restrained their growth. A ...

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Problems solved by technology

[0004] The problem with low-k dielectric materials is that they are not as stiff as traditional dielectric materials

First, since the wires are made of metals (such as copper and tungsten), there is a thermal expansion mismatch between the low-k dielectric and the metal, causing delamination, fracture or destruction of the low-k material during manufacturing or in field use

Second, since the wires are formed through a damascene process, which includes a chemical mechanical polishing (CMP) step, mechanical stress is induced into the device during CMP, causing delamination, fracture or destruction

As sputter etch is applied to the sidewalls of the interlayer dielectric, this results in erosion of the dielectric material, which redeposits on the bottom surface of the via at the interface of the via and the underlying wire, resulting in poor reliability

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