Integrated circuit,method and apparatus for fine tuning clock signals of an integrated circuit

Abstract

The invention provides an integrated circuit and a method and system for adjusting an integrated circuit clocked signal, which comprises a plurality of skew-programmable clock buffer, a fixed phase logic unit, an external interface and a skew controller. Each skew-programmable clock buffer is used for receiving a distributing clocked signal to provide a corresponding local clock signal with a programmed skew. The fixed phase logic unit enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. When using the invention by laser, the best area clock skew of the element can be detected when detecting one element to reach maximum clock speed of the element.

Description

technical field [0001] The present invention relates to the frequency of successive logic blocks on an integrated circuit, especially for fine-tuning and permanently programming the skew of clock signals after critical timing path identification and analysis in debug and test procedures ) method and device. Background technique [0002] Integrated circuit designers have used simulation and / or testing to identify, isolate, and analyze timing problems on chips that, at best, prevent the chip from performing at the target clock speed, but at worst Situations can result in chips that must be modified in design before mass production. Typically, buffer logic cells within each logic block on the chip are used to pass data to subsequent logic stages or to receive data from previous logic stages. If the operation performed by a logic block has an associated critical delay path (critical delay path), and it causes valid data at a specific clock speed, it will not be sent to the loc...

AI Technical Summary

Problems solved by technology

Worse, a sustain time issue at this point would render the chip completely inoperable

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